aarch64: Add the SME2 ADD and SUB instructions
Add support for the SME2 ADD. SUB, FADD and FSUB instructions.
SUB and FSUB have the same form as ADD and FADD, except that
ADD also has a 2-operand accumulating form.
The 64-bit ADD/SUB instructions require FEAT_SME_I16I64 and the
64-bit FADD/FSUB instructions require FEAT_SME_F64F64.
These are the first instructions to have tied register list
operands, as opposed to tied single registers.
The parse_operands change prevents unsuffixed Z registers (width==-1)
from being treated as though they had an Advanced SIMD-style suffix
(.4s etc.). It means that:
Error: expected element type rather than vector type at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'
becomes:
Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'
This commit is contained in:
Richard Sandiford
@@ -6659,6 +6659,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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case AARCH64_OPND_SVE_Zm_16:
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case AARCH64_OPND_SVE_Zn:
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case AARCH64_OPND_SVE_Zt:
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case AARCH64_OPND_SME_Zm:
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reg_type = REG_TYPE_Z;
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goto vector_reg;
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@@ -6811,7 +6812,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
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goto failure;
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}
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if (vectype.width != 0 && *str != ',')
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if ((int) vectype.width > 0 && *str != ',')
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{
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set_fatal_syntax_error
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(_("expected element type rather than vector type"));
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@@ -0,0 +1,3 @@
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#as: -march=armv8-a
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#source: sme2-9-invalid.s
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#error_output: sme2-9-invalid.l
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@@ -0,0 +1,179 @@
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[^ :]+: Assembler messages:
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[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `add 0,{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `add za\.s\[w8,0\],0'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.s\[w8,0\],{z0\.s-z2\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z1\.s-z2\.s}'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z1\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z1\.s-z4\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z2\.s-z5\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z3\.s-z6\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.s\[w8,0,vgx4\],{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.s\[w8,0,vgx2\],{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}
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[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'
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[^ :]+:[0-9]+: Error: expected a register or register list at operand 1 -- `add 0,{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected '{' at operand 2 -- `add za\.s\[w8,0\],0,z0\.s'
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[^ :]+:[0-9]+: Error: expected a register or register list at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},0'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w0,0\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `add za\.s\[w31,0\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,1<<63\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},z31\.s'
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[^ :]+:[0-9]+: Error: the last offset is equal to the first offset at operand 1 -- `add za\.s\[w8,0:0\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: the last offset is less than the first offset at operand 1 -- `add za\.s\[w8,0:-1\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `add za\.s\[w8,0:1\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a single offset rather than a range at operand 1 -- `add za\.s\[w8,0:100\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},z16\.s'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z3\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z3\.s},z0\.s'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z3\.s},z0\.s'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z3\.s},z0\.s'
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[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z3\.s},z16\.s'
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[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.s\[w8,0\],{z0\.s-z2\.s},z0\.s'
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[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `add za\.s\[w8,0\],{z0\.s-z4\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.s\[w8,0\],{z0\.s,z1\.s,z2\.s},z0\.s'
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[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `add za\.s\[w8,0\],{z0\.s,z1\.s,z5\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},z0\.s'
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[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s},z0\.s'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
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[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1},z0\.s'
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[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.s\[w8,0\],{z0\.s-z1\.s},z0'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
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[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s},z0'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z1\.s-z2\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z15\.s-z16\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z31\.s,z0\.s}'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w7,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.s\[w12,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,-1\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.s\[w8,8\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z1\.s-z4\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z2\.s-z5\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.s\[w8,0\],{z3\.s-z6\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z3\.s},{z15\.s-z18\.s}'
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[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z3\.s},{z29\.s,z30\.s,z31\.s,z0\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.s\[w8,0\],{z0\.s-z2\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z2\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `add za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z4\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.s\[w8,0,vgx4\],{z0\.s-z1\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.s\[w8,0,vgx2\],{z0\.s-z3\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
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[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
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[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
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[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z1\.b},{z0\.b-z2\.b},z0\.b'
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[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z1\.b},{z0\.b-z3\.b},z0\.b'
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[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 1 -- `add {z0\.b-z2\.b},{z0\.b-z2\.b},z0\.b'
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[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z1\.b},{z2\.b-z3\.b},z0\.b'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z1\.b-z2\.b},{z1\.b-z2\.b},z0\.b'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z31\.b,z0\.b},{z31\.b,z0\.b},z0\.b'
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[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z1\.b},{z0\.b-z1\.b},z16\.b'
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[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z1\.b},{z0\.b-z1\.b},z31\.b'
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[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z1\.b},{z0\.h-z1\.h},z0\.b'
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[^ :]+:[0-9]+: Info: did you mean this\?
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[^ :]+:[0-9]+: Info: add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
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[^ :]+:[0-9]+: Info: add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h
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[^ :]+:[0-9]+: Info: add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s
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[^ :]+:[0-9]+: Info: add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d
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[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z1\.b},{z0\.b-z1\.b},z0\.h'
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[^ :]+:[0-9]+: Info: did you mean this\?
|
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[^ :]+:[0-9]+: Info: add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
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[^ :]+:[0-9]+: Info: add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h
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[^ :]+:[0-9]+: Info: add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s
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[^ :]+:[0-9]+: Info: add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d
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[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.q-z1\.q},{z0\.q-z1\.q},z0\.q'
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[^ :]+:[0-9]+: Info: did you mean this\?
|
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[^ :]+:[0-9]+: Info: add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b
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[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h
|
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[^ :]+:[0-9]+: Info: add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s
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[^ :]+:[0-9]+: Info: add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d
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[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z3\.b},{z0\.b-z2\.b},z0\.b'
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[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z3\.b},{z0\.b-z1\.b},z0\.b'
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[^ :]+:[0-9]+: Error: operand 2 must be the same register as operand 1 -- `add {z0\.b-z3\.b},{z2\.b-z5\.b},z0\.b'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z1\.b-z4\.b},{z1\.b-z4\.b},z0\.b'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z2\.b-z5\.b},{z2\.b-z5\.b},z0\.b'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z3\.b-z6\.b},{z3\.b-z6\.b},z0\.b'
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[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `add {z31\.b,z0\.b,z1\.b,z2\.b},{z31\.b,z0\.b,z1\.b,z2\.b},z0\.b'
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[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z3\.b},{z0\.b-z3\.b},z16\.b'
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[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add {z0\.b-z3\.b},{z0\.b-z3\.b},z31\.b'
|
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[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z3\.b},{z0\.h-z3\.h},z0\.b'
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[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h
|
||||
[^ :]+:[0-9]+: Info: add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s
|
||||
[^ :]+:[0-9]+: Info: add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.b-z3\.b},{z0\.b-z3\.b},z0\.h'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h
|
||||
[^ :]+:[0-9]+: Info: add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s
|
||||
[^ :]+:[0-9]+: Info: add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `add {z0\.q-z3\.q},{z0\.q-z3\.q},z0\.q'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h
|
||||
[^ :]+:[0-9]+: Info: add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s
|
||||
[^ :]+:[0-9]+: Info: add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d
|
||||
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.b-z1\.b},{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.h-z1\.h},{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.s-z1\.s},{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.d-z1\.d},{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.b-z3\.b},{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.h-z3\.h},{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.s-z3\.s},{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: expected a register at operand 1 -- `sub {z0\.d-z3\.d},{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.b\[w8,0\],{z0\.b-z1\.b}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s}
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d}
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.h\[w8,0\],{z0\.h-z1\.h}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s}
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d}
|
||||
@@ -0,0 +1,128 @@
|
||||
add 0, { z0.s - z1.s }
|
||||
add za.s[w8, 0], 0
|
||||
|
||||
add za.s[w7, 0], { z0.s - z1.s }
|
||||
add za.s[w12, 0], { z0.s - z1.s }
|
||||
add za.s[w8, -1], { z0.s - z1.s }
|
||||
add za.s[w8, 8], { z0.s - z1.s }
|
||||
add za.s[w8, 0], { z0.s - z2.s }
|
||||
add za.s[w8, 0], { z1.s - z2.s }
|
||||
|
||||
add za.s[w7, 0], { z0.s - z3.s }
|
||||
add za.s[w12, 0], { z0.s - z3.s }
|
||||
add za.s[w8, -1], { z0.s - z3.s }
|
||||
add za.s[w8, 8], { z1.s - z3.s }
|
||||
add za.s[w8, 0], { z1.s - z4.s }
|
||||
add za.s[w8, 0], { z2.s - z5.s }
|
||||
add za.s[w8, 0], { z3.s - z6.s }
|
||||
|
||||
add za.s[w8, 0, vgx4], { z0.s - z1.s }
|
||||
add za.s[w8, 0, vgx2], { z0.s - z3.s }
|
||||
add za[w8, 0], { z0.s - z1.s }
|
||||
add za.s[w8, 0], { z0 - z1 }
|
||||
|
||||
add 0, { z0.s - z1.s }, z0.s
|
||||
add za.s[w8, 0], 0, z0.s
|
||||
add za.s[w8, 0], { z0.s - z1.s }, 0
|
||||
|
||||
add za.s[w0, 0], { z0.s - z1.s }, z0.s
|
||||
add za.s[w31, 0], { z0.s - z1.s }, z0.s
|
||||
add za.s[w8, 1<<63], { z0.s - z1.s }, z0.s
|
||||
add za.s[w8, 0], { z0.s - z1.s }, z31.s
|
||||
add za.s[w8, 0:0], { z0.s - z1.s }, z0.s
|
||||
add za.s[w8, 0:-1], { z0.s - z1.s }, z0.s
|
||||
add za.s[w8, 0:1], { z0.s - z1.s }, z0.s
|
||||
add za.s[w8, 0:100], { z0.s - z1.s }, z0.s
|
||||
|
||||
add za.s[w7, 0], { z0.s - z1.s }, z0.s
|
||||
add za.s[w12, 0], { z0.s - z1.s }, z0.s
|
||||
add za.s[w8, -1], { z0.s - z1.s }, z0.s
|
||||
add za.s[w8, 8], { z0.s - z1.s }, z0.s
|
||||
add za.s[w8, 0], { z0.s - z1.s }, z16.s
|
||||
|
||||
add za.s[w7, 0], { z0.s - z3.s }, z0.s
|
||||
add za.s[w12, 0], { z0.s - z3.s }, z0.s
|
||||
add za.s[w8, -1], { z0.s - z3.s }, z0.s
|
||||
add za.s[w8, 8], { z0.s - z3.s }, z0.s
|
||||
add za.s[w8, 0], { z0.s - z3.s }, z16.s
|
||||
|
||||
add za.s[w8, 0], { z0.s - z2.s }, z0.s
|
||||
add za.s[w8, 0], { z0.s - z4.s }, z0.s
|
||||
add za.s[w8, 0], { z0.s, z1.s, z2.s }, z0.s
|
||||
add za.s[w8, 0], { z0.s, z1.s, z5.s }, z0.s
|
||||
|
||||
add za.s[w8, 0, vgx4], { z0.s - z1.s }, z0.s
|
||||
add za.s[w8, 0, vgx2], { z0.s - z3.s }, z0.s
|
||||
add za[w8, 0], { z0.s - z1.s }, z0.s
|
||||
add za.s[w8, 0], { z0 - z1 }, z0.s
|
||||
add za.s[w8, 0], { z0.s - z1.s }, z0
|
||||
add za[w8, 0], { z0.s - z1.s }, z0
|
||||
|
||||
add za.s[w7, 0], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
add za.s[w12, 0], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
add za.s[w8, -1], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
add za.s[w8, 8], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
add za.s[w8, 0], { z1.s - z2.s }, { z0.s - z1.s }
|
||||
add za.s[w8, 0], { z0.s - z1.s }, { z15.s - z16.s }
|
||||
add za.s[w8, 0], { z0.s - z1.s }, { z31.s, z0.s }
|
||||
|
||||
add za.s[w7, 0], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
add za.s[w12, 0], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
add za.s[w8, -1], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
add za.s[w8, 8], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
add za.s[w8, 0], { z1.s - z4.s }, { z0.s - z3.s }
|
||||
add za.s[w8, 0], { z2.s - z5.s }, { z0.s - z3.s }
|
||||
add za.s[w8, 0], { z3.s - z6.s }, { z0.s - z3.s }
|
||||
add za.s[w8, 0], { z0.s - z3.s }, { z15.s - z18.s }
|
||||
add za.s[w8, 0], { z0.s - z3.s }, { z29.s, z30.s, z31.s, z0.s }
|
||||
|
||||
add za.s[w8, 0], { z0.s - z2.s }, { z0.s - z1.s }
|
||||
add za.s[w8, 0], { z0.s - z3.s }, { z0.s - z1.s }
|
||||
add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z2.s }
|
||||
add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z3.s }
|
||||
add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z4.s }
|
||||
|
||||
add za.s[w8, 0, vgx4], { z0.s - z1.s }, { z0.s - z3.s }
|
||||
add za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z1.s }
|
||||
add za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z3.s }
|
||||
add za.s[w8, 0, vgx2], { z0.s - z3.s }, { z0.s - z1.s }
|
||||
add za[w8, 0], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
add za[w8, 0], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
|
||||
add { z0.b - z1.b }, { z0.b - z2.b }, z0.b
|
||||
add { z0.b - z1.b }, { z0.b - z3.b }, z0.b
|
||||
add { z0.b - z2.b }, { z0.b - z2.b }, z0.b
|
||||
add { z0.b - z1.b }, { z2.b - z3.b }, z0.b
|
||||
add { z1.b - z2.b }, { z1.b - z2.b }, z0.b
|
||||
add { z31.b, z0.b }, { z31.b, z0.b }, z0.b
|
||||
add { z0.b - z1.b }, { z0.b - z1.b }, z16.b
|
||||
add { z0.b - z1.b }, { z0.b - z1.b }, z31.b
|
||||
add { z0.b - z1.b }, { z0.h - z1.h }, z0.b
|
||||
add { z0.b - z1.b }, { z0.b - z1.b }, z0.h
|
||||
add { z0.q - z1.q }, { z0.q - z1.q }, z0.q
|
||||
|
||||
add { z0.b - z3.b }, { z0.b - z2.b }, z0.b
|
||||
add { z0.b - z3.b }, { z0.b - z1.b }, z0.b
|
||||
add { z0.b - z3.b }, { z2.b - z5.b }, z0.b
|
||||
add { z1.b - z4.b }, { z1.b - z4.b }, z0.b
|
||||
add { z2.b - z5.b }, { z2.b - z5.b }, z0.b
|
||||
add { z3.b - z6.b }, { z3.b - z6.b }, z0.b
|
||||
add { z31.b, z0.b, z1.b, z2.b }, { z31.b, z0.b, z1.b, z2.b }, z0.b
|
||||
add { z0.b - z3.b }, { z0.b - z3.b }, z16.b
|
||||
add { z0.b - z3.b }, { z0.b - z3.b }, z31.b
|
||||
add { z0.b - z3.b }, { z0.h - z3.h }, z0.b
|
||||
add { z0.b - z3.b }, { z0.b - z3.b }, z0.h
|
||||
add { z0.q - z3.q }, { z0.q - z3.q }, z0.q
|
||||
|
||||
sub { z0.b - z1.b }, { z0.b - z1.b }, z0.b
|
||||
sub { z0.h - z1.h }, { z0.h - z1.h }, z0.h
|
||||
sub { z0.s - z1.s }, { z0.s - z1.s }, z0.s
|
||||
sub { z0.d - z1.d }, { z0.d - z1.d }, z0.d
|
||||
|
||||
sub { z0.b - z3.b }, { z0.b - z3.b }, z0.b
|
||||
sub { z0.h - z3.h }, { z0.h - z3.h }, z0.h
|
||||
sub { z0.s - z3.s }, { z0.s - z3.s }, z0.s
|
||||
sub { z0.d - z3.d }, { z0.d - z3.d }, z0.d
|
||||
|
||||
fadd za.b[w8, 0], { z0.b - z1.b }
|
||||
fadd za.h[w8, 0], { z0.h - z1.h }
|
||||
@@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme
|
||||
#source: sme2-9.s
|
||||
#error_output: sme2-9-noarch.l
|
||||
@@ -0,0 +1,177 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx2\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z30\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w10,3\],{z10\.s-z11\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx4\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z28\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,1\],{z12\.s-z15\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},Z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},Z0\.S'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z31\.s,z0\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z31\.s-z0\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w9,5\],{z9\.s-z10\.s},z6\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},Z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z31\.s-z2\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,2\],{z23\.s-z26\.s},z13\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z30\.s-z31\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z1\.s},{z30\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w10,1\],{z22\.s-z23\.s},{z18\.s-z19\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,7\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z28\.s-z31\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w8,0\],{z0\.s-z3\.s},{z28\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.s\[w11,3\],{z16\.s-z19\.s},{z24\.s-z27\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z1\.b},{z0\.b-z1\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.b-z31\.b},{z30\.b-z31\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z1\.b},{z0\.b-z1\.b},z15\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z14\.b-z15\.b},{z14\.b-z15\.b},z5\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z1\.h},{z0\.h-z1\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.h-z31\.h},{z30\.h-z31\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z1\.h},{z0\.h-z1\.h},z15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z20\.h-z21\.h},{z20\.h-z21\.h},z11\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z1\.s},{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.s-z31\.s},{z30\.s-z31\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z1\.s},{z0\.s-z1\.s},z15\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z2\.s-z3\.s},{z2\.s-z3\.s},z9\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z1\.d},{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z30\.d-z31\.d},{z30\.d-z31\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z1\.d},{z0\.d-z1\.d},z15\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.d-z29\.d},{z28\.d-z29\.d},z1\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z3\.b},{z0\.b-z3\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.b-z31\.b},{z28\.b-z31\.b},z0\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.b-z3\.b},{z0\.b-z3\.b},z15\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z24\.b-z27\.b},{z24\.b-z27\.b},z5\.b'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z3\.h},{z0\.h-z3\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.h-z31\.h},{z28\.h-z31\.h},z0\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.h-z3\.h},{z0\.h-z3\.h},z15\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z20\.h-z23\.h},{z20\.h-z23\.h},z11\.h'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z3\.s},{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.s-z31\.s},{z28\.s-z31\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.s-z3\.s},{z0\.s-z3\.s},z15\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z4\.s-z7\.s},{z4\.s-z7\.s},z9\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z3\.d},{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z28\.d-z31\.d},{z28\.d-z31\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z0\.d-z3\.d},{z0\.d-z3\.d},z15\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add {z16\.d-z19\.d},{z16\.d-z19\.d},z3\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx2\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z30\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w10,3\],{z10\.s-z11\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx4\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z28\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,1\],{z12\.s-z15\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},Z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},Z0\.S'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z1\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z30\.s-z31\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z31\.s,z0\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z31\.s-z0\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s},z15\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w9,5\],{z9\.s-z10\.s},z6\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},Z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},Z0\.S'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z3\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z28\.s-z31\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z31\.s,z0\.s,z1\.s,z2\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z31\.s-z2\.s},z0\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s},z15\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,2\],{z23\.s-z26\.s},z13\.s'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx2\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s},{Z0\.s-Z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S},{Z0\.S-Z1\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z1\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z30\.s-z31\.s},{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z1\.s},{z30\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w10,1\],{z22\.s-z23\.s},{z18\.s-z19\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0,vgx4\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s},{Z0\.s-Z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S},{Z0\.S-Z3\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,0\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,7\],{z0\.s-z3\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z28\.s-z31\.s},{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w8,0\],{z0\.s-z3\.s},{z28\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `sub za\.s\[w11,3\],{z16\.s-z19\.s},{z24\.s-z27\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0,vgx2\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w11,0\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,7\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0\],{z30\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w10,3\],{z10\.s-z11\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0,vgx4\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w11,0\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,7\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w8,0\],{z28\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.s\[w11,1\],{z12\.s-z15\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0,vgx2\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.s\[W8,0,VGx2\],{Z0\.s-Z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.S\[W8,0,VGX2\],{Z0\.S-Z1\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w11,0\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,7\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0\],{z30\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w10,3\],{z10\.s-z11\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0,vgx4\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.s\[W8,0,VGx4\],{Z0\.s-Z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.S\[W8,0,VGX4\],{Z0\.S-Z3\.S}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w11,0\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,7\],{z0\.s-z3\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w8,0\],{z28\.s-z31\.s}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.s\[w11,1\],{z12\.s-z15\.s}'
|
||||
@@ -0,0 +1,185 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c10 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a07c10 add za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c17 add za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01fd0 add za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}
|
||||
[^:]+: c1a05d53 add za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s}
|
||||
[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c10 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a17c10 add za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c17 add za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11f90 add za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}
|
||||
[^:]+: c1a17d91 add za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s}
|
||||
[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1207810 add za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201817 add za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201bd0 add za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s
|
||||
[^:]+: c1201bf0 add za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
|
||||
[^:]+: c1201bf0 add za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
|
||||
[^:]+: c12f1810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s
|
||||
[^:]+: c1263935 add za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s
|
||||
[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1307810 add za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301817 add za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301b90 add za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s
|
||||
[^:]+: c1301bf0 add za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
|
||||
[^:]+: c1301bf0 add za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
|
||||
[^:]+: c13f1810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s
|
||||
[^:]+: c13d7af2 add za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s
|
||||
[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a07810 add za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01817 add za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01bd0 add za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1be1810 add za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s}
|
||||
[^:]+: c1b25ad1 add za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.s}
|
||||
[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a17810 add za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11817 add za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11b90 add za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1bd1810 add za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s}
|
||||
[^:]+: c1b97a13 add za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.s}
|
||||
[^:]+: c120a300 add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z0\.b
|
||||
[^:]+: c120a31e add {z30\.b-z31\.b}, {z30\.b-z31\.b}, z0\.b
|
||||
[^:]+: c12fa300 add {z0\.b-z1\.b}, {z0\.b-z1\.b}, z15\.b
|
||||
[^:]+: c125a30e add {z14\.b-z15\.b}, {z14\.b-z15\.b}, z5\.b
|
||||
[^:]+: c160a300 add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z0\.h
|
||||
[^:]+: c160a31e add {z30\.h-z31\.h}, {z30\.h-z31\.h}, z0\.h
|
||||
[^:]+: c16fa300 add {z0\.h-z1\.h}, {z0\.h-z1\.h}, z15\.h
|
||||
[^:]+: c16ba314 add {z20\.h-z21\.h}, {z20\.h-z21\.h}, z11\.h
|
||||
[^:]+: c1a0a300 add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1a0a31e add {z30\.s-z31\.s}, {z30\.s-z31\.s}, z0\.s
|
||||
[^:]+: c1afa300 add {z0\.s-z1\.s}, {z0\.s-z1\.s}, z15\.s
|
||||
[^:]+: c1a9a302 add {z2\.s-z3\.s}, {z2\.s-z3\.s}, z9\.s
|
||||
[^:]+: c1e0a300 add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1e0a31e add {z30\.d-z31\.d}, {z30\.d-z31\.d}, z0\.d
|
||||
[^:]+: c1efa300 add {z0\.d-z1\.d}, {z0\.d-z1\.d}, z15\.d
|
||||
[^:]+: c1e1a31c add {z28\.d-z29\.d}, {z28\.d-z29\.d}, z1\.d
|
||||
[^:]+: c120ab00 add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z0\.b
|
||||
[^:]+: c120ab1c add {z28\.b-z31\.b}, {z28\.b-z31\.b}, z0\.b
|
||||
[^:]+: c12fab00 add {z0\.b-z3\.b}, {z0\.b-z3\.b}, z15\.b
|
||||
[^:]+: c125ab18 add {z24\.b-z27\.b}, {z24\.b-z27\.b}, z5\.b
|
||||
[^:]+: c160ab00 add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z0\.h
|
||||
[^:]+: c160ab1c add {z28\.h-z31\.h}, {z28\.h-z31\.h}, z0\.h
|
||||
[^:]+: c16fab00 add {z0\.h-z3\.h}, {z0\.h-z3\.h}, z15\.h
|
||||
[^:]+: c16bab14 add {z20\.h-z23\.h}, {z20\.h-z23\.h}, z11\.h
|
||||
[^:]+: c1a0ab00 add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1a0ab1c add {z28\.s-z31\.s}, {z28\.s-z31\.s}, z0\.s
|
||||
[^:]+: c1afab00 add {z0\.s-z3\.s}, {z0\.s-z3\.s}, z15\.s
|
||||
[^:]+: c1a9ab04 add {z4\.s-z7\.s}, {z4\.s-z7\.s}, z9\.s
|
||||
[^:]+: c1e0ab00 add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1e0ab1c add {z28\.d-z31\.d}, {z28\.d-z31\.d}, z0\.d
|
||||
[^:]+: c1efab00 add {z0\.d-z3\.d}, {z0\.d-z3\.d}, z15\.d
|
||||
[^:]+: c1e3ab10 add {z16\.d-z19\.d}, {z16\.d-z19\.d}, z3\.d
|
||||
[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c18 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a07c18 sub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c1f sub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01fd8 sub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}
|
||||
[^:]+: c1a05d5b sub za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s}
|
||||
[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c18 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a17c18 sub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c1f sub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11f98 sub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}
|
||||
[^:]+: c1a17d99 sub za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s}
|
||||
[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1207818 sub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c120181f sub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, z0\.s
|
||||
[^:]+: c1201bd8 sub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, z0\.s
|
||||
[^:]+: c1201bf8 sub za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
|
||||
[^:]+: c1201bf8 sub za\.s\[w8, 0, vgx2\], {z31\.s-z0\.s}, z0\.s
|
||||
[^:]+: c12f1818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, z15\.s
|
||||
[^:]+: c126393d sub za\.s\[w9, 5, vgx2\], {z9\.s-z10\.s}, z6\.s
|
||||
[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1307818 sub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c130181f sub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, z0\.s
|
||||
[^:]+: c1301b98 sub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, z0\.s
|
||||
[^:]+: c1301bf8 sub za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
|
||||
[^:]+: c1301bf8 sub za\.s\[w8, 0, vgx4\], {z31\.s-z2\.s}, z0\.s
|
||||
[^:]+: c13f1818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, z15\.s
|
||||
[^:]+: c13d7afa sub za\.s\[w11, 2, vgx4\], {z23\.s-z26\.s}, z13\.s
|
||||
[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a07818 sub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a0181f sub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1a01bd8 sub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}, {z0\.s-z1\.s}
|
||||
[^:]+: c1be1818 sub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}, {z30\.s-z31\.s}
|
||||
[^:]+: c1b25ad9 sub za\.s\[w10, 1, vgx2\], {z22\.s-z23\.s}, {z18\.s-z19\.s}
|
||||
[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a17818 sub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a1181f sub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1a11b98 sub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}, {z0\.s-z3\.s}
|
||||
[^:]+: c1bd1818 sub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}, {z28\.s-z31\.s}
|
||||
[^:]+: c1b97a1b sub za\.s\[w11, 3, vgx4\], {z16\.s-z19\.s}, {z24\.s-z27\.s}
|
||||
[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c00 fadd za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a07c00 fadd za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c07 fadd za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01fc0 fadd za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}
|
||||
[^:]+: c1a05d43 fadd za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s}
|
||||
[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c00 fadd za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a17c00 fadd za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c07 fadd za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11f80 fadd za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}
|
||||
[^:]+: c1a17d81 fadd za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s}
|
||||
[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c08 fsub za\.s\[w8, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a07c08 fsub za\.s\[w11, 0, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01c0f fsub za\.s\[w8, 7, vgx2\], {z0\.s-z1\.s}
|
||||
[^:]+: c1a01fc8 fsub za\.s\[w8, 0, vgx2\], {z30\.s-z31\.s}
|
||||
[^:]+: c1a05d4b fsub za\.s\[w10, 3, vgx2\], {z10\.s-z11\.s}
|
||||
[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c08 fsub za\.s\[w8, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a17c08 fsub za\.s\[w11, 0, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11c0f fsub za\.s\[w8, 7, vgx4\], {z0\.s-z3\.s}
|
||||
[^:]+: c1a11f88 fsub za\.s\[w8, 0, vgx4\], {z28\.s-z31\.s}
|
||||
[^:]+: c1a17d89 fsub za\.s\[w11, 1, vgx4\], {z12\.s-z15\.s}
|
||||
@@ -0,0 +1,199 @@
|
||||
add za.s[w8, 0], { z0.s - z1.s }
|
||||
add za.s[w8, 0, vgx2], { z0.s - z1.s }
|
||||
ADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }
|
||||
ADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }
|
||||
add za.s[w11, 0], { z0.s - z1.s }
|
||||
add za.s[w8, 7], { z0.s - z1.s }
|
||||
add za.s[w8, 0], { z30.s - z31.s }
|
||||
add za.s[w10, 3], { z10.s - z11.s }
|
||||
|
||||
add za.s[w8, 0], { z0.s - z3.s }
|
||||
add za.s[w8, 0, vgx4], { z0.s - z3.s }
|
||||
ADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }
|
||||
ADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }
|
||||
add za.s[w11, 0], { z0.s - z3.s }
|
||||
add za.s[w8, 7], { z0.s - z3.s }
|
||||
add za.s[w8, 0], { z28.s - z31.s }
|
||||
add za.s[w11, 1], { z12.s - z15.s }
|
||||
|
||||
add za.s[w8, 0], { z0.s - z1.s }, z0.s
|
||||
add za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s
|
||||
ADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s
|
||||
ADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S
|
||||
add za.s[w11, 0], { z0.s - z1.s }, z0.s
|
||||
add za.s[w8, 7], { z0.s - z1.s }, z0.s
|
||||
add za.s[w8, 0], { z30.s - z31.s }, z0.s
|
||||
add za.s[w8, 0], { z31.s, z0.s }, z0.s
|
||||
add za.s[w8, 0], { z31.s - z0.s }, z0.s
|
||||
add za.s[w8, 0], { z0.s - z1.s }, z15.s
|
||||
add za.s[w9, 5], { z9.s - z10.s }, z6.s
|
||||
|
||||
add za.s[w8, 0], { z0.s - z3.s }, z0.s
|
||||
add za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
|
||||
ADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s
|
||||
ADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S
|
||||
add za.s[w11, 0], { z0.s - z3.s }, z0.s
|
||||
add za.s[w8, 7], { z0.s - z3.s }, z0.s
|
||||
add za.s[w8, 0], { z28.s - z31.s }, z0.s
|
||||
add za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s
|
||||
add za.s[w8, 0], { z31.s - z2.s }, z0.s
|
||||
add za.s[w8, 0], { z0.s - z3.s }, z15.s
|
||||
add za.s[w11, 2], { z23.s - z26.s }, z13.s
|
||||
|
||||
add za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
add za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
ADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s }
|
||||
ADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S }
|
||||
add za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
add za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
add za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s }
|
||||
add za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s }
|
||||
add za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s }
|
||||
|
||||
add za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
add za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
ADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s }
|
||||
ADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S }
|
||||
add za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
add za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
add za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s }
|
||||
add za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s }
|
||||
add za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s }
|
||||
|
||||
add { z0.b - z1.b }, { z0.b - z1.b }, z0.b
|
||||
add { z30.b - z31.b }, { z30.b - z31.b }, z0.b
|
||||
add { z0.b - z1.b }, { z0.b - z1.b }, z15.b
|
||||
add { z14.b - z15.b }, { z14.b - z15.b }, z5.b
|
||||
|
||||
add { z0.h - z1.h }, { z0.h - z1.h }, z0.h
|
||||
add { z30.h - z31.h }, { z30.h - z31.h }, z0.h
|
||||
add { z0.h - z1.h }, { z0.h - z1.h }, z15.h
|
||||
add { z20.h - z21.h }, { z20.h - z21.h }, z11.h
|
||||
|
||||
add { z0.s - z1.s }, { z0.s - z1.s }, z0.s
|
||||
add { z30.s - z31.s }, { z30.s - z31.s }, z0.s
|
||||
add { z0.s - z1.s }, { z0.s - z1.s }, z15.s
|
||||
add { z2.s - z3.s }, { z2.s - z3.s }, z9.s
|
||||
|
||||
add { z0.d - z1.d }, { z0.d - z1.d }, z0.d
|
||||
add { z30.d - z31.d }, { z30.d - z31.d }, z0.d
|
||||
add { z0.d - z1.d }, { z0.d - z1.d }, z15.d
|
||||
add { z28.d - z29.d }, { z28.d - z29.d }, z1.d
|
||||
|
||||
add { z0.b - z3.b }, { z0.b - z3.b }, z0.b
|
||||
add { z28.b - z31.b }, { z28.b - z31.b }, z0.b
|
||||
add { z0.b - z3.b }, { z0.b - z3.b }, z15.b
|
||||
add { z24.b - z27.b }, { z24.b - z27.b }, z5.b
|
||||
|
||||
add { z0.h - z3.h }, { z0.h - z3.h }, z0.h
|
||||
add { z28.h - z31.h }, { z28.h - z31.h }, z0.h
|
||||
add { z0.h - z3.h }, { z0.h - z3.h }, z15.h
|
||||
add { z20.h - z23.h }, { z20.h - z23.h }, z11.h
|
||||
|
||||
add { z0.s - z3.s }, { z0.s - z3.s }, z0.s
|
||||
add { z28.s - z31.s }, { z28.s - z31.s }, z0.s
|
||||
add { z0.s - z3.s }, { z0.s - z3.s }, z15.s
|
||||
add { z4.s - z7.s }, { z4.s - z7.s }, z9.s
|
||||
|
||||
add { z0.d - z3.d }, { z0.d - z3.d }, z0.d
|
||||
add { z28.d - z31.d }, { z28.d - z31.d }, z0.d
|
||||
add { z0.d - z3.d }, { z0.d - z3.d }, z15.d
|
||||
add { z16.d - z19.d }, { z16.d - z19.d }, z3.d
|
||||
|
||||
sub za.s[w8, 0], { z0.s - z1.s }
|
||||
sub za.s[w8, 0, vgx2], { z0.s - z1.s }
|
||||
SUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }
|
||||
SUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }
|
||||
sub za.s[w11, 0], { z0.s - z1.s }
|
||||
sub za.s[w8, 7], { z0.s - z1.s }
|
||||
sub za.s[w8, 0], { z30.s - z31.s }
|
||||
sub za.s[w10, 3], { z10.s - z11.s }
|
||||
|
||||
sub za.s[w8, 0], { z0.s - z3.s }
|
||||
sub za.s[w8, 0, vgx4], { z0.s - z3.s }
|
||||
SUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }
|
||||
SUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }
|
||||
sub za.s[w11, 0], { z0.s - z3.s }
|
||||
sub za.s[w8, 7], { z0.s - z3.s }
|
||||
sub za.s[w8, 0], { z28.s - z31.s }
|
||||
sub za.s[w11, 1], { z12.s - z15.s }
|
||||
|
||||
sub za.s[w8, 0], { z0.s - z1.s }, z0.s
|
||||
sub za.s[w8, 0, vgx2], { z0.s - z1.s }, z0.s
|
||||
SUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, Z0.s
|
||||
SUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, Z0.S
|
||||
sub za.s[w11, 0], { z0.s - z1.s }, z0.s
|
||||
sub za.s[w8, 7], { z0.s - z1.s }, z0.s
|
||||
sub za.s[w8, 0], { z30.s - z31.s }, z0.s
|
||||
sub za.s[w8, 0], { z31.s, z0.s }, z0.s
|
||||
sub za.s[w8, 0], { z31.s - z0.s }, z0.s
|
||||
sub za.s[w8, 0], { z0.s - z1.s }, z15.s
|
||||
sub za.s[w9, 5], { z9.s - z10.s }, z6.s
|
||||
|
||||
sub za.s[w8, 0], { z0.s - z3.s }, z0.s
|
||||
sub za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
|
||||
SUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, Z0.s
|
||||
SUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, Z0.S
|
||||
sub za.s[w11, 0], { z0.s - z3.s }, z0.s
|
||||
sub za.s[w8, 7], { z0.s - z3.s }, z0.s
|
||||
sub za.s[w8, 0], { z28.s - z31.s }, z0.s
|
||||
sub za.s[w8, 0], { z31.s, z0.s, z1.s, z2.s }, z0.s
|
||||
sub za.s[w8, 0], { z31.s - z2.s }, z0.s
|
||||
sub za.s[w8, 0], { z0.s - z3.s }, z15.s
|
||||
sub za.s[w11, 2], { z23.s - z26.s }, z13.s
|
||||
|
||||
sub za.s[w8, 0], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
sub za.s[w8, 0, vgx2], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
SUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }, { Z0.s - Z1.s }
|
||||
SUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }, { Z0.S - Z1.S }
|
||||
sub za.s[w11, 0], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
sub za.s[w8, 7], { z0.s - z1.s }, { z0.s - z1.s }
|
||||
sub za.s[w8, 0], { z30.s - z31.s }, { z0.s - z1.s }
|
||||
sub za.s[w8, 0], { z0.s - z1.s }, { z30.s - z31.s }
|
||||
sub za.s[w10, 1], { z22.s - z23.s }, { z18.s - z19.s }
|
||||
|
||||
sub za.s[w8, 0], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
sub za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
SUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }, { Z0.s - Z3.s }
|
||||
SUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }, { Z0.S - Z3.S }
|
||||
sub za.s[w11, 0], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
sub za.s[w8, 7], { z0.s - z3.s }, { z0.s - z3.s }
|
||||
sub za.s[w8, 0], { z28.s - z31.s }, { z0.s - z3.s }
|
||||
sub za.s[w8, 0], { z0.s - z3.s }, { z28.s - z31.s }
|
||||
sub za.s[w11, 3], { z16.s - z19.s }, { z24.s - z27.s }
|
||||
|
||||
fadd za.s[w8, 0], { z0.s - z1.s }
|
||||
fadd za.s[w8, 0, vgx2], { z0.s - z1.s }
|
||||
FADD ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }
|
||||
FADD ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }
|
||||
fadd za.s[w11, 0], { z0.s - z1.s }
|
||||
fadd za.s[w8, 7], { z0.s - z1.s }
|
||||
fadd za.s[w8, 0], { z30.s - z31.s }
|
||||
fadd za.s[w10, 3], { z10.s - z11.s }
|
||||
|
||||
fadd za.s[w8, 0], { z0.s - z3.s }
|
||||
fadd za.s[w8, 0, vgx4], { z0.s - z3.s }
|
||||
FADD ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }
|
||||
FADD ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }
|
||||
fadd za.s[w11, 0], { z0.s - z3.s }
|
||||
fadd za.s[w8, 7], { z0.s - z3.s }
|
||||
fadd za.s[w8, 0], { z28.s - z31.s }
|
||||
fadd za.s[w11, 1], { z12.s - z15.s }
|
||||
|
||||
fsub za.s[w8, 0], { z0.s - z1.s }
|
||||
fsub za.s[w8, 0, vgx2], { z0.s - z1.s }
|
||||
FSUB ZA.s[W8, 0, VGx2], { Z0.s - Z1.s }
|
||||
FSUB ZA.S[W8, 0, VGX2], { Z0.S - Z1.S }
|
||||
fsub za.s[w11, 0], { z0.s - z1.s }
|
||||
fsub za.s[w8, 7], { z0.s - z1.s }
|
||||
fsub za.s[w8, 0], { z30.s - z31.s }
|
||||
fsub za.s[w10, 3], { z10.s - z11.s }
|
||||
|
||||
fsub za.s[w8, 0], { z0.s - z3.s }
|
||||
fsub za.s[w8, 0, vgx4], { z0.s - z3.s }
|
||||
FSUB ZA.s[W8, 0, VGx4], { Z0.s - Z3.s }
|
||||
FSUB ZA.S[W8, 0, VGX4], { Z0.S - Z3.S }
|
||||
fsub za.s[w11, 0], { z0.s - z3.s }
|
||||
fsub za.s[w8, 7], { z0.s - z3.s }
|
||||
fsub za.s[w8, 0], { z28.s - z31.s }
|
||||
fsub za.s[w11, 1], { z12.s - z15.s }
|
||||
@@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a
|
||||
#source: sme2-f64f64-1-invalid.s
|
||||
#error_output: sme2-f64f64-1-invalid.l
|
||||
@@ -0,0 +1,27 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.d\[w7,0\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.d\[w12,0\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.d\[w8,-1\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.d\[w8,8\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `fadd za\.d\[w8,0\],{z0\.d-z2\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za\.d\[w8,0\],{z1\.d-z2\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.d\[w7,0\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `fadd za\.d\[w12,0\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.d\[w8,-1\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `fadd za\.d\[w8,8\],{z1\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za\.d\[w8,0\],{z1\.d-z4\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za\.d\[w8,0\],{z2\.d-z5\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `fadd za\.d\[w8,0\],{z3\.d-z6\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `fadd za\.d\[w8,0,vgx4\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `fadd za\.d\[w8,0,vgx2\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\[w8,0\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d}
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s}
|
||||
[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `fadd za\.d\[w8,0\],{z0-z1}'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `fadd za\.d\[w8,0\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: fadd za\.s\[w8, 0\], {z0\.s-z1\.s}
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: fadd za\.d\[w8, 0\], {z0\.d-z1\.d}
|
||||
@@ -0,0 +1,20 @@
|
||||
fadd za.d[w7, 0], { z0.d - z1.d }
|
||||
fadd za.d[w12, 0], { z0.d - z1.d }
|
||||
fadd za.d[w8, -1], { z0.d - z1.d }
|
||||
fadd za.d[w8, 8], { z0.d - z1.d }
|
||||
fadd za.d[w8, 0], { z0.d - z2.d }
|
||||
fadd za.d[w8, 0], { z1.d - z2.d }
|
||||
|
||||
fadd za.d[w7, 0], { z0.d - z3.d }
|
||||
fadd za.d[w12, 0], { z0.d - z3.d }
|
||||
fadd za.d[w8, -1], { z0.d - z3.d }
|
||||
fadd za.d[w8, 8], { z1.d - z3.d }
|
||||
fadd za.d[w8, 0], { z1.d - z4.d }
|
||||
fadd za.d[w8, 0], { z2.d - z5.d }
|
||||
fadd za.d[w8, 0], { z3.d - z6.d }
|
||||
|
||||
fadd za.d[w8, 0, vgx4], { z0.d - z1.d }
|
||||
fadd za.d[w8, 0, vgx2], { z0.d - z3.d }
|
||||
fadd za[w8, 0], { z0.d - z1.d }
|
||||
fadd za.d[w8, 0], { z0 - z1 }
|
||||
fadd za.d[w8, 0], { z0.s - z1.s }
|
||||
@@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#source: sme2-f64f64-1.s
|
||||
#error_output: sme2-f64f64-1-noarch.l
|
||||
@@ -0,0 +1,33 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0,vgx2\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w11,0\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,7\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0\],{z30\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w10,3\],{z10\.d-z11\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0,vgx4\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w11,0\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,7\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w8,0\],{z28\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fadd za\.d\[w11,1\],{z12\.d-z15\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0,vgx2\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w11,0\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,7\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0\],{z30\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w10,3\],{z10\.d-z11\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0,vgx4\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w11,0\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,7\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w8,0\],{z28\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `fsub za\.d\[w11,1\],{z12\.d-z15\.d}'
|
||||
@@ -0,0 +1,41 @@
|
||||
#as: -march=armv8-a+sme2+sme-f64f64
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01c00 fadd za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e07c00 fadd za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01c07 fadd za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01fc0 fadd za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}
|
||||
[^:]+: c1e05d43 fadd za\.d\[w10, 3, vgx2\], {z10\.d-z11\.d}
|
||||
[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11c00 fadd za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e17c00 fadd za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11c07 fadd za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11f80 fadd za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}
|
||||
[^:]+: c1e17d81 fadd za\.d\[w11, 1, vgx4\], {z12\.d-z15\.d}
|
||||
[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01c08 fsub za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e07c08 fsub za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01c0f fsub za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01fc8 fsub za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}
|
||||
[^:]+: c1e05d4b fsub za\.d\[w10, 3, vgx2\], {z10\.d-z11\.d}
|
||||
[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11c08 fsub za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e17c08 fsub za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11c0f fsub za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11f88 fsub za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}
|
||||
[^:]+: c1e17d89 fsub za\.d\[w11, 1, vgx4\], {z12\.d-z15\.d}
|
||||
@@ -0,0 +1,35 @@
|
||||
fadd za.d[w8, 0], { z0.d - z1.d }
|
||||
fadd za.d[w8, 0, vgx2], { z0.d - z1.d }
|
||||
FADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }
|
||||
FADD ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }
|
||||
fadd za.d[w11, 0], { z0.d - z1.d }
|
||||
fadd za.d[w8, 7], { z0.d - z1.d }
|
||||
fadd za.d[w8, 0], { z30.d - z31.d }
|
||||
fadd za.d[w10, 3], { z10.d - z11.d }
|
||||
|
||||
fadd za.d[w8, 0], { z0.d - z3.d }
|
||||
fadd za.d[w8, 0, vgx4], { z0.d - z3.d }
|
||||
FADD ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }
|
||||
FADD ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }
|
||||
fadd za.d[w11, 0], { z0.d - z3.d }
|
||||
fadd za.d[w8, 7], { z0.d - z3.d }
|
||||
fadd za.d[w8, 0], { z28.d - z31.d }
|
||||
fadd za.d[w11, 1], { z12.d - z15.d }
|
||||
|
||||
fsub za.d[w8, 0], { z0.d - z1.d }
|
||||
fsub za.d[w8, 0, vgx2], { z0.d - z1.d }
|
||||
FSUB ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }
|
||||
FSUB ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }
|
||||
fsub za.d[w11, 0], { z0.d - z1.d }
|
||||
fsub za.d[w8, 7], { z0.d - z1.d }
|
||||
fsub za.d[w8, 0], { z30.d - z31.d }
|
||||
fsub za.d[w10, 3], { z10.d - z11.d }
|
||||
|
||||
fsub za.d[w8, 0], { z0.d - z3.d }
|
||||
fsub za.d[w8, 0, vgx4], { z0.d - z3.d }
|
||||
FSUB ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }
|
||||
FSUB ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }
|
||||
fsub za.d[w11, 0], { z0.d - z3.d }
|
||||
fsub za.d[w8, 7], { z0.d - z3.d }
|
||||
fsub za.d[w8, 0], { z28.d - z31.d }
|
||||
fsub za.d[w11, 1], { z12.d - z15.d }
|
||||
@@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a
|
||||
#source: sme2-i16i64-1-invalid.s
|
||||
#error_output: sme2-i16i64-1-invalid.l
|
||||
@@ -0,0 +1,111 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.d\[w8,0\],{z0\.d-z2\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z1\.d-z2\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z1\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z1\.d-z4\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z2\.d-z5\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z3\.d-z6\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.d\[w8,0,vgx4\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.d\[w8,0,vgx2\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}
|
||||
[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.d\[w8,0\],{z0-z1}'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.d\[w8,0\],{z0\.s-z1\.s}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w0,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `add za\.d\[w31,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,1<<63\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},z31\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},z16\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: z0-z15 expected at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z3\.d},z16\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.d\[w8,0\],{z0\.d-z2\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 2 -- `add za\.d\[w8,0\],{z0\.d-z4\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.d\[w8,0\],{z0\.d,z1\.d,z2\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: invalid register list at operand 2 -- `add za\.d\[w8,0\],{z0\.d,z1\.d,z5\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
|
||||
[^ :]+:[0-9]+: Error: missing type suffix at operand 2 -- `add za\.d\[w8,0\],{z0-z1},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.d\[w8,0\],{z0\.d-z1\.d},z0'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d},z0'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.s\[w8,0\],{z0\.d-z1\.d},z0\.s'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `add za\.d\[w8,0\],{z0\.s-z1\.s},z0\.d'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, z0\.d
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, z0\.s
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w0,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a 32-bit selection register at operand 1 -- `add za\.d\[w31,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,1<<63\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z1\.d-z2\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z15\.d-z16\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z31\.d,z0\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w7,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a selection register in the range w8-w11 at operand 1 -- `add za\.d\[w12,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,-1\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: immediate offset out of range 0 to 7 at operand 1 -- `add za\.d\[w8,8\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z1\.d-z4\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z2\.d-z5\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 2 -- `add za\.d\[w8,0\],{z3\.d-z6\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z3\.d},{z15\.d-z18\.d}'
|
||||
[^ :]+:[0-9]+: Error: start register out of range at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z3\.d},{z29\.d,z30\.d,z31\.d,z0\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 or 4 registers at operand 2 -- `add za\.d\[w8,0\],{z0\.d-z2\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z2\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: too many registers in vector register list at operand 3 -- `add za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z4\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 2 -- `add za\.d\[w8,0,vgx4\],{z0\.d-z1\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 3 -- `add za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 3 -- `add za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: expected a list of 2 registers at operand 2 -- `add za\.d\[w8,0,vgx2\],{z0\.d-z3\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z1\.s}, {z0\.s-z1\.s}
|
||||
[^ :]+:[0-9]+: Error: operand mismatch -- `add za\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Info: did you mean this\?
|
||||
[^ :]+:[0-9]+: Info: add za\.d\[w8, 0\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^ :]+:[0-9]+: Info: other valid variant\(s\):
|
||||
[^ :]+:[0-9]+: Info: add za\.s\[w8, 0\], {z0\.s-z3\.s}, {z0\.s-z3\.s}
|
||||
@@ -0,0 +1,86 @@
|
||||
add za.d[w7, 0], { z0.d - z1.d }
|
||||
add za.d[w12, 0], { z0.d - z1.d }
|
||||
add za.d[w8, -1], { z0.d - z1.d }
|
||||
add za.d[w8, 8], { z0.d - z1.d }
|
||||
add za.d[w8, 0], { z0.d - z2.d }
|
||||
add za.d[w8, 0], { z1.d - z2.d }
|
||||
|
||||
add za.d[w7, 0], { z0.d - z3.d }
|
||||
add za.d[w12, 0], { z0.d - z3.d }
|
||||
add za.d[w8, -1], { z0.d - z3.d }
|
||||
add za.d[w8, 8], { z1.d - z3.d }
|
||||
add za.d[w8, 0], { z1.d - z4.d }
|
||||
add za.d[w8, 0], { z2.d - z5.d }
|
||||
add za.d[w8, 0], { z3.d - z6.d }
|
||||
|
||||
add za.d[w8, 0, vgx4], { z0.d - z1.d }
|
||||
add za.d[w8, 0, vgx2], { z0.d - z3.d }
|
||||
add za[w8, 0], { z0.d - z1.d }
|
||||
add za.d[w8, 0], { z0 - z1 }
|
||||
add za.d[w8, 0], { z0.s - z1.s }
|
||||
|
||||
add za.d[w0, 0], { z0.d - z1.d }, z0.d
|
||||
add za.d[w31, 0], { z0.d - z1.d }, z0.d
|
||||
add za.d[w8, 1<<63], { z0.d - z1.d }, z0.d
|
||||
add za.d[w8, 0], { z0.d - z1.d }, z31.d
|
||||
|
||||
add za.d[w7, 0], { z0.d - z1.d }, z0.d
|
||||
add za.d[w12, 0], { z0.d - z1.d }, z0.d
|
||||
add za.d[w8, -1], { z0.d - z1.d }, z0.d
|
||||
add za.d[w8, 8], { z0.d - z1.d }, z0.d
|
||||
add za.d[w8, 0], { z0.d - z1.d }, z16.d
|
||||
|
||||
add za.d[w7, 0], { z0.d - z3.d }, z0.d
|
||||
add za.d[w12, 0], { z0.d - z3.d }, z0.d
|
||||
add za.d[w8, -1], { z0.d - z3.d }, z0.d
|
||||
add za.d[w8, 8], { z0.d - z3.d }, z0.d
|
||||
add za.d[w8, 0], { z0.d - z3.d }, z16.d
|
||||
|
||||
add za.d[w8, 0], { z0.d - z2.d }, z0.d
|
||||
add za.d[w8, 0], { z0.d - z4.d }, z0.d
|
||||
add za.d[w8, 0], { z0.d, z1.d, z2.d }, z0.d
|
||||
add za.d[w8, 0], { z0.d, z1.d, z5.d }, z0.d
|
||||
|
||||
add za.d[w8, 0, vgx4], { z0.d - z1.d }, z0.d
|
||||
add za.d[w8, 0, vgx2], { z0.d - z3.d }, z0.d
|
||||
add za[w8, 0], { z0.d - z1.d }, z0.d
|
||||
add za.d[w8, 0], { z0 - z1 }, z0.d
|
||||
add za.d[w8, 0], { z0.d - z1.d }, z0
|
||||
add za[w8, 0], { z0.d - z1.d }, z0
|
||||
add za.s[w8, 0], { z0.d - z1.d }, z0.s
|
||||
add za.d[w8, 0], { z0.s - z1.s }, z0.d
|
||||
|
||||
add za.d[w0, 0], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
add za.d[w31, 0], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
add za.d[w8, 1<<63], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
|
||||
add za.d[w7, 0], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
add za.d[w12, 0], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
add za.d[w8, -1], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
add za.d[w8, 8], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
add za.d[w8, 8], { z1.d - z2.d }, { z0.d - z1.d }
|
||||
add za.d[w8, 0], { z0.d - z1.d }, { z15.d - z16.d }
|
||||
add za.d[w8, 0], { z0.d - z1.d }, { z31.d, z0.d }
|
||||
|
||||
add za.d[w7, 0], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
add za.d[w12, 0], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
add za.d[w8, -1], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
add za.d[w8, 8], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
add za.d[w8, 0], { z1.d - z4.d }, { z0.d - z3.d }
|
||||
add za.d[w8, 0], { z2.d - z5.d }, { z0.d - z3.d }
|
||||
add za.d[w8, 0], { z3.d - z6.d }, { z0.d - z3.d }
|
||||
add za.d[w8, 0], { z0.d - z3.d }, { z15.d - z18.d }
|
||||
add za.d[w8, 0], { z0.d - z3.d }, { z29.d, z30.d, z31.d, z0.d }
|
||||
|
||||
add za.d[w8, 0], { z0.d - z2.d }, { z0.d - z1.d }
|
||||
add za.d[w8, 0], { z0.d - z3.d }, { z0.d - z1.d }
|
||||
add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z2.d }
|
||||
add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z3.d }
|
||||
add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z4.d }
|
||||
|
||||
add za.d[w8, 0, vgx4], { z0.d - z1.d }, { z0.d - z3.d }
|
||||
add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z1.d }
|
||||
add za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z3.d }
|
||||
add za.d[w8, 0, vgx2], { z0.d - z3.d }, { z0.d - z1.d }
|
||||
add za[w8, 0], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
add za[w8, 0], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
@@ -0,0 +1,3 @@
|
||||
#as: -march=armv8-a+sme2
|
||||
#source: sme2-i16i64-1.s
|
||||
#error_output: sme2-i16i64-1-noarch.l
|
||||
@@ -0,0 +1,57 @@
|
||||
[^ :]+: Assembler messages:
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx2\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z30\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w10,3\],{z10\.d-z11\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx4\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z28\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,1\],{z12\.d-z15\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},Z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},Z0\.D'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z1\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z30\.d-z31\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z31\.d,z0\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z31\.d-z0\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d},z15\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w9,5\],{z9\.d-z10\.d},z6\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},Z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},Z0\.D'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z3\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z28\.d-z31\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z31\.d,z0\.d,z1\.d,z2\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z31\.d-z2\.d},z0\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d},z15\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,2\],{z23\.d-z26\.d},z13\.d'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx2\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx2\],{Z0\.d-Z1\.d},{Z0\.d-Z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX2\],{Z0\.D-Z1\.D},{Z0\.D-Z1\.D}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z1\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z30\.d-z31\.d},{z0\.d-z1\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z1\.d},{z30\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w10,1\],{z22\.d-z23\.d},{z18\.d-z19\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0,vgx4\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.d\[W8,0,VGx4\],{Z0\.d-Z3\.d},{Z0\.d-Z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add ZA\.D\[W8,0,VGX4\],{Z0\.D-Z3\.D},{Z0\.D-Z3\.D}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,0\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,7\],{z0\.d-z3\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z28\.d-z31\.d},{z0\.d-z3\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w8,0\],{z0\.d-z3\.d},{z28\.d-z31\.d}'
|
||||
[^ :]+:[0-9]+: Error: selected processor does not support `add za\.d\[w11,3\],{z16\.d-z19\.d},{z24\.d-z27\.d}'
|
||||
@@ -0,0 +1,65 @@
|
||||
#as: -march=armv8-a+sme2+sme-i16i64
|
||||
#objdump: -dr
|
||||
|
||||
[^:]+: file format .*
|
||||
|
||||
|
||||
[^:]+:
|
||||
|
||||
[^:]+:
|
||||
[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01c10 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e07c10 add za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01c17 add za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}
|
||||
[^:]+: c1e01fd0 add za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}
|
||||
[^:]+: c1e05d53 add za\.d\[w10, 3, vgx2\], {z10\.d-z11\.d}
|
||||
[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11c10 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e17c10 add za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11c17 add za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}
|
||||
[^:]+: c1e11f90 add za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}
|
||||
[^:]+: c1e17d91 add za\.d\[w11, 1, vgx4\], {z12\.d-z15\.d}
|
||||
[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1601810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1607810 add za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1601817 add za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, z0\.d
|
||||
[^:]+: c1601bd0 add za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, z0\.d
|
||||
[^:]+: c1601bf0 add za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d
|
||||
[^:]+: c1601bf0 add za\.d\[w8, 0, vgx2\], {z31\.d-z0\.d}, z0\.d
|
||||
[^:]+: c16f1810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, z15\.d
|
||||
[^:]+: c1663935 add za\.d\[w9, 5, vgx2\], {z9\.d-z10\.d}, z6\.d
|
||||
[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1701810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1707810 add za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1701817 add za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, z0\.d
|
||||
[^:]+: c1701b90 add za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, z0\.d
|
||||
[^:]+: c1701bf0 add za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d
|
||||
[^:]+: c1701bf0 add za\.d\[w8, 0, vgx4\], {z31\.d-z2\.d}, z0\.d
|
||||
[^:]+: c17f1810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, z15\.d
|
||||
[^:]+: c17d7af2 add za\.d\[w11, 2, vgx4\], {z23\.d-z26\.d}, z13\.d
|
||||
[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e01810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e07810 add za\.d\[w11, 0, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e01817 add za\.d\[w8, 7, vgx2\], {z0\.d-z1\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1e01bd0 add za\.d\[w8, 0, vgx2\], {z30\.d-z31\.d}, {z0\.d-z1\.d}
|
||||
[^:]+: c1fe1810 add za\.d\[w8, 0, vgx2\], {z0\.d-z1\.d}, {z30\.d-z31\.d}
|
||||
[^:]+: c1f25ad1 add za\.d\[w10, 1, vgx2\], {z22\.d-z23\.d}, {z18\.d-z19\.d}
|
||||
[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e11810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e17810 add za\.d\[w11, 0, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e11817 add za\.d\[w8, 7, vgx4\], {z0\.d-z3\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1e11b90 add za\.d\[w8, 0, vgx4\], {z28\.d-z31\.d}, {z0\.d-z3\.d}
|
||||
[^:]+: c1fd1810 add za\.d\[w8, 0, vgx4\], {z0\.d-z3\.d}, {z28\.d-z31\.d}
|
||||
[^:]+: c1f97a13 add za\.d\[w11, 3, vgx4\], {z16\.d-z19\.d}, {z24\.d-z27\.d}
|
||||
@@ -0,0 +1,61 @@
|
||||
add za.d[w8, 0], { z0.d - z1.d }
|
||||
add za.d[w8, 0, vgx2], { z0.d - z1.d }
|
||||
ADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }
|
||||
ADD ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }
|
||||
add za.d[w11, 0], { z0.d - z1.d }
|
||||
add za.d[w8, 7], { z0.d - z1.d }
|
||||
add za.d[w8, 0], { z30.d - z31.d }
|
||||
add za.d[w10, 3], { z10.d - z11.d }
|
||||
|
||||
add za.d[w8, 0], { z0.d - z3.d }
|
||||
add za.d[w8, 0, vgx4], { z0.d - z3.d }
|
||||
ADD ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }
|
||||
ADD ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }
|
||||
add za.d[w11, 0], { z0.d - z3.d }
|
||||
add za.d[w8, 7], { z0.d - z3.d }
|
||||
add za.d[w8, 0], { z28.d - z31.d }
|
||||
add za.d[w11, 1], { z12.d - z15.d }
|
||||
|
||||
add za.d[w8, 0], { z0.d - z1.d }, z0.d
|
||||
add za.d[w8, 0, vgx2], { z0.d - z1.d }, z0.d
|
||||
ADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, Z0.d
|
||||
ADD ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, Z0.D
|
||||
add za.d[w11, 0], { z0.d - z1.d }, z0.d
|
||||
add za.d[w8, 7], { z0.d - z1.d }, z0.d
|
||||
add za.d[w8, 0], { z30.d - z31.d }, z0.d
|
||||
add za.d[w8, 0], { z31.d, z0.d }, z0.d
|
||||
add za.d[w8, 0], { z31.d - z0.d }, z0.d
|
||||
add za.d[w8, 0], { z0.d - z1.d }, z15.d
|
||||
add za.d[w9, 5], { z9.d - z10.d }, z6.d
|
||||
|
||||
add za.d[w8, 0], { z0.d - z3.d }, z0.d
|
||||
add za.d[w8, 0, vgx4], { z0.d - z3.d }, z0.d
|
||||
ADD ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, Z0.d
|
||||
ADD ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, Z0.D
|
||||
add za.d[w11, 0], { z0.d - z3.d }, z0.d
|
||||
add za.d[w8, 7], { z0.d - z3.d }, z0.d
|
||||
add za.d[w8, 0], { z28.d - z31.d }, z0.d
|
||||
add za.d[w8, 0], { z31.d, z0.d, z1.d, z2.d }, z0.d
|
||||
add za.d[w8, 0], { z31.d - z2.d }, z0.d
|
||||
add za.d[w8, 0], { z0.d - z3.d }, z15.d
|
||||
add za.d[w11, 2], { z23.d - z26.d }, z13.d
|
||||
|
||||
add za.d[w8, 0], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
add za.d[w8, 0, vgx2], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
ADD ZA.d[W8, 0, VGx2], { Z0.d - Z1.d }, { Z0.d - Z1.d }
|
||||
ADD ZA.D[W8, 0, VGX2], { Z0.D - Z1.D }, { Z0.D - Z1.D }
|
||||
add za.d[w11, 0], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
add za.d[w8, 7], { z0.d - z1.d }, { z0.d - z1.d }
|
||||
add za.d[w8, 0], { z30.d - z31.d }, { z0.d - z1.d }
|
||||
add za.d[w8, 0], { z0.d - z1.d }, { z30.d - z31.d }
|
||||
add za.d[w10, 1], { z22.d - z23.d }, { z18.d - z19.d }
|
||||
|
||||
add za.d[w8, 0], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
add za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
ADD ZA.d[W8, 0, VGx4], { Z0.d - Z3.d }, { Z0.d - Z3.d }
|
||||
ADD ZA.D[W8, 0, VGX4], { Z0.D - Z3.D }, { Z0.D - Z3.D }
|
||||
add za.d[w11, 0], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
add za.d[w8, 7], { z0.d - z3.d }, { z0.d - z3.d }
|
||||
add za.d[w8, 0], { z28.d - z31.d }, { z0.d - z3.d }
|
||||
add za.d[w8, 0], { z0.d - z3.d }, { z28.d - z31.d }
|
||||
add za.d[w11, 3], { z16.d - z19.d }, { z24.d - z27.d }
|
||||
@@ -487,6 +487,7 @@ enum aarch64_opnd
|
||||
AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
|
||||
AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */
|
||||
AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */
|
||||
AARCH64_OPND_SME_Zm, /* SVE vector register list in 4-bit Zm. */
|
||||
AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */
|
||||
AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */
|
||||
AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */
|
||||
@@ -695,6 +696,8 @@ enum aarch64_insn_class
|
||||
movewide,
|
||||
pcreladdr,
|
||||
ic_system,
|
||||
sme_fp_sd,
|
||||
sme_int_sd,
|
||||
sme_misc,
|
||||
sme_mov,
|
||||
sme_ldr,
|
||||
|
||||
+26
-25
@@ -667,12 +667,13 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 203:
|
||||
case 209:
|
||||
case 212:
|
||||
case 222:
|
||||
case 216:
|
||||
case 223:
|
||||
case 230:
|
||||
case 224:
|
||||
case 231:
|
||||
case 232:
|
||||
case 233:
|
||||
case 234:
|
||||
return aarch64_ins_regno (self, info, code, inst, errors);
|
||||
case 15:
|
||||
return aarch64_ins_reg_extended (self, info, code, inst, errors);
|
||||
@@ -684,7 +685,7 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 33:
|
||||
case 34:
|
||||
case 35:
|
||||
case 256:
|
||||
case 257:
|
||||
return aarch64_ins_reglane (self, info, code, inst, errors);
|
||||
case 36:
|
||||
return aarch64_ins_reglist (self, info, code, inst, errors);
|
||||
@@ -729,13 +730,13 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 192:
|
||||
case 193:
|
||||
case 194:
|
||||
case 236:
|
||||
case 250:
|
||||
case 237:
|
||||
case 251:
|
||||
case 253:
|
||||
case 255:
|
||||
case 260:
|
||||
case 252:
|
||||
case 254:
|
||||
case 256:
|
||||
case 261:
|
||||
case 262:
|
||||
return aarch64_ins_imm (self, info, code, inst, errors);
|
||||
case 44:
|
||||
case 45:
|
||||
@@ -804,8 +805,8 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
case 107:
|
||||
return aarch64_ins_prfop (self, info, code, inst, errors);
|
||||
case 108:
|
||||
case 252:
|
||||
case 254:
|
||||
case 253:
|
||||
case 255:
|
||||
return aarch64_ins_none (self, info, code, inst, errors);
|
||||
case 109:
|
||||
return aarch64_ins_hint (self, info, code, inst, errors);
|
||||
@@ -896,48 +897,48 @@ aarch64_insert_operand (const aarch64_operand *self,
|
||||
return aarch64_ins_sve_index (self, info, code, inst, errors);
|
||||
case 211:
|
||||
case 213:
|
||||
case 229:
|
||||
case 230:
|
||||
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
|
||||
case 214:
|
||||
case 215:
|
||||
case 216:
|
||||
case 217:
|
||||
case 218:
|
||||
case 219:
|
||||
case 228:
|
||||
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
|
||||
case 220:
|
||||
case 229:
|
||||
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
|
||||
case 221:
|
||||
case 222:
|
||||
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
|
||||
case 224:
|
||||
case 226:
|
||||
case 237:
|
||||
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
|
||||
case 225:
|
||||
case 227:
|
||||
case 238:
|
||||
return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
|
||||
case 226:
|
||||
case 228:
|
||||
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
|
||||
case 234:
|
||||
case 235:
|
||||
case 244:
|
||||
case 236:
|
||||
case 245:
|
||||
case 246:
|
||||
case 247:
|
||||
case 248:
|
||||
case 249:
|
||||
case 250:
|
||||
return aarch64_ins_simple_index (self, info, code, inst, errors);
|
||||
case 238:
|
||||
case 239:
|
||||
case 240:
|
||||
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
|
||||
case 241:
|
||||
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
|
||||
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
|
||||
case 242:
|
||||
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
|
||||
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
|
||||
case 243:
|
||||
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
|
||||
case 244:
|
||||
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
|
||||
case 257:
|
||||
case 258:
|
||||
case 259:
|
||||
case 260:
|
||||
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
|
||||
default: assert (0); abort ();
|
||||
}
|
||||
|
||||
@@ -2008,6 +2008,8 @@ aarch64_encode_variant_using_iclass (struct aarch64_inst *inst)
|
||||
insert_field (FLD_size, &inst->value, aarch64_get_variant (inst) % 3 + 1, 0);
|
||||
break;
|
||||
|
||||
case sme_fp_sd:
|
||||
case sme_int_sd:
|
||||
case sve_size_bh:
|
||||
case sve_size_sd:
|
||||
insert_field (FLD_SVE_sz, &inst->value, aarch64_get_variant (inst), 0);
|
||||
|
||||
+644
-445
File diff suppressed because it is too large
Load Diff
@@ -3169,6 +3169,8 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
|
||||
variant = i - 1;
|
||||
break;
|
||||
|
||||
case sme_fp_sd:
|
||||
case sme_int_sd:
|
||||
case sve_size_bh:
|
||||
case sve_size_sd:
|
||||
variant = extract_field (FLD_SVE_sz, inst->value, 0);
|
||||
|
||||
@@ -240,6 +240,7 @@ const struct aarch64_operand aarch64_operands[] =
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm}, "an SVE vector register"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4}, "a list of SVE vector registers"},
|
||||
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2}, "a list of SVE vector registers"},
|
||||
|
||||
+54
-17
@@ -241,6 +241,7 @@ const aarch64_field fields[] =
|
||||
{ 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
|
||||
{ 1, 4 }, /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */
|
||||
{ 2, 3 }, /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */
|
||||
{ 16, 4 }, /* SME_Zm: Z0-Z15, bits [19:16]. */
|
||||
{ 17, 4 }, /* SME_Zm2: Z0-Z31, multiple of 2, bits [20:17]. */
|
||||
{ 18, 3 }, /* SME_Zm4: Z0-Z31, multiple of 4, bits [20:18]. */
|
||||
{ 6, 4 }, /* SME_Zn2: Z0-Z31, multiple of 2, bits [9:6]. */
|
||||
@@ -1764,6 +1765,14 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
|
||||
return 0;
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_Zm:
|
||||
if (opnd->reg.regno > 15)
|
||||
{
|
||||
set_invalid_regno_error (mismatch_detail, idx, "z", 0, 15);
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
|
||||
case AARCH64_OPND_SME_PnT_Wm_imm:
|
||||
size = aarch64_get_qualifier_esize (opnd->qualifier);
|
||||
max_value = 16 / size - 1;
|
||||
@@ -3101,23 +3110,38 @@ aarch64_match_operands_constraint (aarch64_inst *inst,
|
||||
break;
|
||||
|
||||
default:
|
||||
/* Check for cases where a source register needs to be the same as the
|
||||
destination register. Do this before matching qualifiers since if
|
||||
an instruction has both invalid tying and invalid qualifiers,
|
||||
the error about qualifiers would suggest several alternative
|
||||
instructions that also have invalid tying. */
|
||||
if (inst->operands[0].reg.regno
|
||||
!= inst->operands[i].reg.regno)
|
||||
{
|
||||
if (mismatch_detail)
|
||||
{
|
||||
mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
|
||||
mismatch_detail->index = i;
|
||||
mismatch_detail->error = NULL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
{
|
||||
/* Check for cases where a source register needs to be the
|
||||
same as the destination register. Do this before
|
||||
matching qualifiers since if an instruction has both
|
||||
invalid tying and invalid qualifiers, the error about
|
||||
qualifiers would suggest several alternative instructions
|
||||
that also have invalid tying. */
|
||||
enum aarch64_operand_class op_class1
|
||||
= aarch64_get_operand_class (inst->operands[0].type);
|
||||
enum aarch64_operand_class op_class2
|
||||
= aarch64_get_operand_class (inst->operands[i].type);
|
||||
assert (op_class1 == op_class2);
|
||||
if (op_class1 == AARCH64_OPND_CLASS_SVE_REGLIST
|
||||
? ((inst->operands[0].reglist.first_regno
|
||||
!= inst->operands[i].reglist.first_regno)
|
||||
|| (inst->operands[0].reglist.num_regs
|
||||
!= inst->operands[i].reglist.num_regs)
|
||||
|| (inst->operands[0].reglist.stride
|
||||
!= inst->operands[i].reglist.stride))
|
||||
: (inst->operands[0].reg.regno
|
||||
!= inst->operands[i].reg.regno))
|
||||
{
|
||||
if (mismatch_detail)
|
||||
{
|
||||
mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
|
||||
mismatch_detail->index = i;
|
||||
mismatch_detail->error = NULL;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -3874,6 +3898,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
|
||||
case AARCH64_OPND_SVE_Zm_16:
|
||||
case AARCH64_OPND_SVE_Zn:
|
||||
case AARCH64_OPND_SVE_Zt:
|
||||
case AARCH64_OPND_SME_Zm:
|
||||
if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
|
||||
snprintf (buf, size, "%s", style_reg (styler, "z%d", opnd->reg.regno));
|
||||
else
|
||||
@@ -6501,6 +6526,18 @@ aarch64_cpu_supports_inst_p (uint64_t cpu_variant, aarch64_inst *inst)
|
||||
|| !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant, *inst->opcode->avariant))
|
||||
return false;
|
||||
|
||||
if (inst->opcode->iclass == sme_fp_sd
|
||||
&& inst->operands[0].qualifier == AARCH64_OPND_QLF_S_D
|
||||
&& !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant,
|
||||
AARCH64_FEATURE_SME_F64F64))
|
||||
return false;
|
||||
|
||||
if (inst->opcode->iclass == sme_int_sd
|
||||
&& inst->operands[0].qualifier == AARCH64_OPND_QLF_S_D
|
||||
&& !AARCH64_CPU_HAS_ALL_FEATURES (cpu_variant,
|
||||
AARCH64_FEATURE_SME_I16I64))
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
|
||||
@@ -62,6 +62,7 @@ enum aarch64_field_kind
|
||||
FLD_SME_ZAda_3b,
|
||||
FLD_SME_Zdn2,
|
||||
FLD_SME_Zdn4,
|
||||
FLD_SME_Zm,
|
||||
FLD_SME_Zm2,
|
||||
FLD_SME_Zm4,
|
||||
FLD_SME_Zn2,
|
||||
|
||||
@@ -5325,7 +5325,19 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("whilelt", 0x25205410, 0xff20fc11, sme_size_22, 0, OP3 (SME_Pdx2, Rn, Rm), OP_SVE_VXX_BHSD, 0, 0),
|
||||
|
||||
/* SME2 extensions to SME. */
|
||||
SME2_INSN ("add", 0xc1a01c10, 0xffbf9c38, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("add", 0xc1a11c10, 0xffbf9c78, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("add", 0xc1201810, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("add", 0xc1301810, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("add", 0xc1a01810, 0xffa19c38, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("add", 0xc1a11810, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("add", 0xc120a300, 0xff30ffe1, sme_size_22, 0, OP3 (SME_Zdnx2, SME_Zdnx2, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
|
||||
SME2_INSN ("add", 0xc120ab00, 0xff30ffe3, sme_size_22, 0, OP3 (SME_Zdnx4, SME_Zdnx4, SME_Zm), OP_SVE_VVV_BHSD, 0, 1),
|
||||
SME2_INSN ("cntp", 0x25208200, 0xff3ffa00, sme_size_22, 0, OP3 (Rd, SME_PNn, SME_VLxN_10), OP_SVE_XV_BHSD, 0, 0),
|
||||
SME2_INSN ("fadd", 0xc1a01c00, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("fadd", 0xc1a11c00, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("fsub", 0xc1a01c08, 0xffbf9c38, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("fsub", 0xc1a11c08, 0xffbf9c78, sme_fp_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("ld1b", 0xa0400000, 0xfff0e001, sve_misc, 0, OP3 (SME_Zdnx2, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ld1b", 0xa0408000, 0xfff0e003, sve_misc, 0, OP3 (SME_Zdnx4, SME_PNg3, SVE_ADDR_RI_S4x4xVL), OP_SVE_BZU, 0, 0),
|
||||
SME2_INSN ("ld1b", 0xa1400000, 0xfff0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RI_S4x2xVL), OP_SVE_BZU, 0, 0),
|
||||
@@ -5485,6 +5497,12 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
SME2_INSN ("stnt1w", 0xa1204008, 0xffe0e008, sve_misc, 0, OP3 (SME_Ztx2_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("stnt1w", 0xa120c008, 0xffe0e00c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_PNg3, SVE_ADDR_RR_LSL2), OP_SVE_SUU, 0, 0),
|
||||
SME2_INSN ("str", 0xe13f8000, 0xfffffc1f, sme_misc, 0, OP2 (SME_ZT0, SIMD_ADDR_SIMPLE), {}, 0, 0),
|
||||
SME2_INSN ("sub", 0xc1a01c18, 0xffbf9c38, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("sub", 0xc1a11c18, 0xffbf9c78, sme_int_sd, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("sub", 0xc1201818, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("sub", 0xc1301818, 0xffb09c18, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SVE_ZnxN, SME_Zm), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("sub", 0xc1a01818, 0xffa19c38, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zmx2), OP_SVE_VVV_SD, F_OD (2), 0),
|
||||
SME2_INSN ("sub", 0xc1a11818, 0xffa39c78, sme_int_sd, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zmx4), OP_SVE_VVV_SD, F_OD (4), 0),
|
||||
SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("whilegt", 0x25204018, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
SME2_INSN ("whilehi", 0x25204818, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),
|
||||
@@ -6138,6 +6156,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
|
||||
F(FLD_SME_Zdn2), "a list of SVE vector registers") \
|
||||
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx4", 4 << OPD_F_OD_LSB, \
|
||||
F(FLD_SME_Zdn4), "a list of SVE vector registers") \
|
||||
Y(SVE_REG, regno, "SME_Zm", 0, F(FLD_SME_Zm), \
|
||||
"an SVE vector register") \
|
||||
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2", 2 << OPD_F_OD_LSB, \
|
||||
F(FLD_SME_Zm2), "a list of SVE vector registers") \
|
||||
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx4", 4 << OPD_F_OD_LSB, \
|
||||
|
||||
Reference in New Issue
Block a user