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Support Intel PREFETCHI

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gas/ChangeLog:

	* NEWS: Add support for Intel PREFETCHI instruction.
	* config/tc-i386.c (load_insn_p): Use prefetch* to fold all prefetches.
	(md_assemble): Add warning for illegal input of PREFETCHI.
	* doc/c-i386.texi: Document .prefetchi.
	* testsuite/gas/i386/i386.exp: Run PREFETCHI tests.
	* testsuite/gas/i386/x86-64-lfence-load.d: Add PREFETCHI.
	* testsuite/gas/i386/x86-64-lfence-load.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetch.d: New test.
	* testsuite/gas/i386/x86-64-prefetchi-intel.d: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-inval-register.d: Likewise..
	* testsuite/gas/i386/x86-64-prefetchi-inval-register.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-warn.l: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi-warn.s: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi.d: Likewise.
	* testsuite/gas/i386/x86-64-prefetchi.s: Likewise.

opcodes/ChangeLog:

	* i386-dis.c (reg_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7
	(x86_64_table): Add X86_64_0F18_REG_6_MOD_0 and X86_64_0F18_REG_7_MOD_0.
	(mod_table): Add MOD_0F18_REG_6 and MOD_0F18_REG_7.
	(prefix_table): Add PREFIX_0F18_REG_6_MOD_0_X86_64 and
	PREFIX_0F18_REG_7_MOD_0_X86_64.
	(PREFETCHI_Fixup): New.
	* i386-gen.c (cpu_flag_init): Add CPU_PREFETCHI_FLAGS.
	(cpu_flags): Add CpuPREFETCHI.
	* i386-opc.h (CpuPREFETCHI): New.
	(i386_cpu_flags): Add cpuprefetchi.
	* i386-opc.tbl: Add Intel PREFETCHI instructions.
	* i386-init.h: Regenerated.
	* i386-tbl.h: Likewise.
This commit is contained in:
Cui, Lili
2022-10-31 21:07:17 +08:00
committed by Cui,Lili
parent 1e74163639
commit ef07be453e
19 changed files with 4366 additions and 4144 deletions
Download Patch File Download Diff File Expand all files Collapse all files
gas/NEWS
+2
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@@ -1,5 +1,7 @@
-*- text -*-
* Add support for Intel PREFETCHI instructions.
* Add support for Intel AMX-FP16 instructions.
* gas now supports --compress-debug-sections=zstd to compress
gas/config/tc-i386.c
+8 -3
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@@ -1095,6 +1095,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (uintr, UINTR, ANY_UINTR, false),
SUBARCH (hreset, HRESET, ANY_HRESET, false),
SUBARCH (avx512_fp16, AVX512_FP16, ANY_AVX512_FP16, false),
SUBARCH (prefetchi, PREFETCHI, PREFETCHI, false),
};
#undef SUBARCH
@@ -4496,9 +4497,8 @@ load_insn_p (void)
if (!any_vex_p)
{
/* Anysize insns: lea, invlpg, clflush, prefetchnta, prefetcht0,
prefetcht1, prefetcht2, prefetchtw, bndmk, bndcl, bndcu, bndcn,
bndstx, bndldx, prefetchwt1, clflushopt, clwb, cldemote. */
/* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
if (i.tm.opcode_modifier.anysize)
return 0;
@@ -5033,6 +5033,11 @@ md_assemble (char *line)
if (!process_suffix ())
return;
/* Check if IP-relative addressing requirements can be satisfied. */
if (i.tm.cpu_flags.bitfield.cpuprefetchi
&& !(i.base_reg && i.base_reg->reg_num == RegIP))
as_warn (_("only support RIP-relative address"), i.tm.name);
/* Update operand types and check extended states. */
for (j = 0; j < i.operands; j++)
{
gas/doc/c-i386.texi
+2
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@@ -194,6 +194,7 @@ accept various extension mnemonics. For example,
@code{avx512_bf16},
@code{avx_vnni},
@code{avx512_fp16},
@code{prefetchi},
@code{amx_int8},
@code{amx_bf16},
@code{amx_fp16},
@@ -1487,6 +1488,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
@item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16}
@item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
@item @samp{.prefetchi}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
gas/testsuite/gas/i386/i386.exp
+4
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@@ -1177,6 +1177,10 @@ if [gas_64_check] then {
run_dump_test "x86-64-tdx"
run_dump_test "x86-64-tsxldtrk"
run_dump_test "x86-64-hreset"
run_dump_test "x86-64-prefetchi"
run_dump_test "x86-64-prefetchi-intel"
run_dump_test "x86-64-prefetchi-inval-register"
run_list_test "x86-64-prefetchi-warn"
run_dump_test "x86-64-vp2intersect"
run_dump_test "x86-64-vp2intersect-intel"
run_list_test "x86-64-vp2intersect-inval-bcast"
gas/testsuite/gas/i386/x86-64-lfence-load.d
+2
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@@ -33,6 +33,8 @@ Disassembly of section .text:
+[a-f0-9]+: 0f 18 55 00 prefetcht1 0x0\(%rbp\)
+[a-f0-9]+: 0f 18 5d 00 prefetcht2 0x0\(%rbp\)
+[a-f0-9]+: 0f 0d 4d 00 prefetchw 0x0\(%rbp\)
+[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
+[a-f0-9]+: 0f a1 pop %fs
+[a-f0-9]+: 0f ae e8 lfence
+[a-f0-9]+: 9d popf
gas/testsuite/gas/i386/x86-64-lfence-load.s
+2
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@@ -20,6 +20,8 @@ _start:
prefetcht1 (%rbp)
prefetcht2 (%rbp)
prefetchw (%rbp)
prefetchit0 0x12345678(%rip)
prefetchit1 0x12345678(%rip)
pop %fs
popf
xlatb (%rbx)
gas/testsuite/gas/i386/x86-64-prefetchi-intel.d
+16
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@@ -0,0 +1,16 @@
#as:
#objdump: -dwMintel
#name: x86-64 PREFETCHI insns (Intel disassembly)
#source: x86-64-prefetchi.s
.*: +file format .*
Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 BYTE PTR \[rip\+0x12345678\] # [0-9a-f]+ <_start\+0x[0-9a-f]+>
#pass
gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.d
+13
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@@ -0,0 +1,13 @@
#as:
#objdump: -dw
#name: x86-64 PREFETCHI INVAL REGISTER insns
.*: +file format .*
Disassembly of section .text:
0+ <\.text>:
[ ]*[a-f0-9]+:[ ]0f 18 39[ ]*nopl \(%rcx\)
[ ]*[a-f0-9]+:[ ]0f 18 31[ ]*nopl \(%rcx\)
#pass
gas/testsuite/gas/i386/x86-64-prefetchi-inval-register.s
+9
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@@ -0,0 +1,9 @@
.text
#prefetchit0 (%rcx) PREFETCHIT0/1 apply without RIP-relative addressing, should stay NOPs.
.byte 0x0f
.byte 0x18
.byte 0x39
#prefetchit1 (%rcx) PREFETCHIT1/1 apply without RIP-relative addressing, should stay NOPs.
.byte 0x0f
.byte 0x18
.byte 0x31
gas/testsuite/gas/i386/x86-64-prefetchi-warn.l
+5
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@@ -0,0 +1,5 @@
.*: Assembler messages:
.*:[0-9]*: Warning: only support RIP-relative address
.*:[0-9]*: Warning: only support RIP-relative address
.*:[0-9]*: Warning: only support RIP-relative address
.*:[0-9]*: Warning: only support RIP-relative address
gas/testsuite/gas/i386/x86-64-prefetchi-warn.s
+11
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@@ -0,0 +1,11 @@
# Check error for ICACHE-PREFETCH 64-bit instruction
.allow_index_reg
.text
_start:
prefetchit0 0x12345678(%rax)
prefetchit1 0x12345678(%rax)
.intel_syntax noprefix
prefetchit0 BYTE PTR [rax+0x12345678]
prefetchit1 BYTE PTR [rax+0x12345678]
gas/testsuite/gas/i386/x86-64-prefetchi.d
+15
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@@ -0,0 +1,15 @@
#as:
#objdump: -dw
#name: x86-64 PREFETCHI insns
.*: +file format .*
Disassembly of section .text:
0+ <_start>:
[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
[ ]*[a-f0-9]+: 0f 18 3d 78 56 34 12 prefetchit0 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
[ ]*[a-f0-9]+: 0f 18 35 78 56 34 12 prefetchit1 0x12345678\(%rip\) # [0-9a-f]+ <_start\+0x[0-9a-f]+>
#pass
gas/testsuite/gas/i386/x86-64-prefetchi.s
+14
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@@ -0,0 +1,14 @@
# Check 64bit PREFETCHI instructions
.allow_index_reg
.text
_start:
prefetchit0 0x12345678(%rip)
prefetchit1 0x12345678(%rip)
.intel_syntax noprefix
prefetchit0 BYTE PTR [rip+0x12345678]
prefetchit1 BYTE PTR [rip+0x12345678]
opcodes/i386-dis.c
+76 -2
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@@ -114,6 +114,7 @@ static void FXSAVE_Fixup (instr_info *, int, int);
static void MOVSXD_Fixup (instr_info *, int, int);
static void DistinctDest_Fixup (instr_info *, int, int);
static void PREFETCHI_Fixup (instr_info *, int, int);
/* This character is used to encode style information within the output
buffers. See oappend_insert_style for more details. */
@@ -840,6 +841,8 @@ enum
MOD_0F18_REG_1,
MOD_0F18_REG_2,
MOD_0F18_REG_3,
MOD_0F18_REG_6,
MOD_0F18_REG_7,
MOD_0F1A_PREFIX_0,
MOD_0F1B_PREFIX_0,
MOD_0F1B_PREFIX_1,
@@ -1002,6 +1005,8 @@ enum
PREFIX_0F11,
PREFIX_0F12,
PREFIX_0F16,
PREFIX_0F18_REG_6_MOD_0_X86_64,
PREFIX_0F18_REG_7_MOD_0_X86_64,
PREFIX_0F1A,
PREFIX_0F1B,
PREFIX_0F1C,
@@ -1268,6 +1273,8 @@ enum
X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
X86_64_0F18_REG_6_MOD_0,
X86_64_0F18_REG_7_MOD_0,
X86_64_0F24,
X86_64_0F26,
X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
@@ -2720,8 +2727,8 @@ static const struct dis386 reg_table[][8] = {
{ MOD_TABLE (MOD_0F18_REG_3) },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ MOD_TABLE (MOD_0F18_REG_6) },
{ MOD_TABLE (MOD_0F18_REG_7) },
},
/* REG_0F1C_P_0_MOD_0 */
{
@@ -3079,6 +3086,22 @@ static const struct dis386 prefix_table[][4] = {
{ MOD_TABLE (MOD_0F16_PREFIX_2) },
},
/* PREFIX_0F18_REG_6_MOD_0_X86_64 */
{
{ "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
},
/* PREFIX_0F18_REG_7_MOD_0_X86_64 */
{
{ "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
},
/* PREFIX_0F1A */
{
{ MOD_TABLE (MOD_0F1A_PREFIX_0) },
@@ -4299,6 +4322,18 @@ static const struct dis386 x86_64_table[][2] = {
{ "psmash", { Skip_MODRM }, 0 },
},
/* X86_64_0F18_REG_6_MOD_0 */
{
{ "nopQ", { Ev }, 0 },
{ PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
},
/* X86_64_0F18_REG_7_MOD_0 */
{
{ "nopQ", { Ev }, 0 },
{ PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
},
{
/* X86_64_0F24 */
{ "movZ", { Em, Td }, 0 },
@@ -7980,6 +8015,16 @@ static const struct dis386 mod_table[][2] = {
{ "prefetcht2", { Mb }, 0 },
{ "nopQ", { Ev }, 0 },
},
{
/* MOD_0F18_REG_6 */
{ X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
{ "nopQ", { Ev }, 0 },
},
{
/* MOD_0F18_REG_7 */
{ X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
{ "nopQ", { Ev }, 0 },
},
{
/* MOD_0F1A_PREFIX_0 */
{ "bndldx", { Gbnd, Mv_bnd }, 0 },
@@ -13752,3 +13797,32 @@ OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
}
oappend (ins, "sae}");
}
static void
PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
{
if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
{
if (ins->intel_syntax)
{
ins->mnemonicendp = stpcpy (ins->obuf, "nop ");
}
else
{
USED_REX (REX_W);
if (ins->rex & REX_W)
ins->mnemonicendp = stpcpy (ins->obuf, "nopq ");
else
{
if (sizeflag & DFLAG)
ins->mnemonicendp = stpcpy (ins->obuf, "nopl ");
else
ins->mnemonicendp = stpcpy (ins->obuf, "nopw ");
ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
}
}
bytemode = v_mode;
}
OP_M (ins, bytemode, sizeflag);
}
opcodes/i386-gen.c
+3
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@@ -245,6 +245,8 @@ static initializer cpu_flag_init[] =
"CPU_AVX512F_FLAGS|CpuAVX512_BF16" },
{ "CPU_AVX512_FP16_FLAGS",
"CPU_AVX512BW_FLAGS|CpuAVX512_FP16" },
{ "CPU_PREFETCHI_FLAGS",
"CpuPREFETCHI"},
{ "CPU_IAMCU_FLAGS",
"Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuIAMCU" },
{ "CPU_ADX_FLAGS",
@@ -642,6 +644,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuTDX),
BITFIELD (CpuAVX_VNNI),
BITFIELD (CpuAVX512_FP16),
BITFIELD (CpuPREFETCHI),
BITFIELD (CpuMWAITX),
BITFIELD (CpuCLZERO),
BITFIELD (CpuOSPKE),
opcodes/i386-init.h
+261 -252
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File diff suppressed because it is too large Load Diff
opcodes/i386-opc.h
+3
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@@ -209,6 +209,8 @@ enum
CpuAVX_VNNI,
/* Intel AVX-512 FP16 Instructions support required. */
CpuAVX512_FP16,
/* PREFETCHI instruction required */
CpuPREFETCHI,
/* mwaitx instruction required */
CpuMWAITX,
/* Clzero instruction required */
@@ -390,6 +392,7 @@ typedef union i386_cpu_flags
unsigned int cputdx:1;
unsigned int cpuavx_vnni:1;
unsigned int cpuavx512_fp16:1;
unsigned int cpuprefetchi:1;
unsigned int cpumwaitx:1;
unsigned int cpuclzero:1;
unsigned int cpuospke:1;
opcodes/i386-opc.tbl
+7
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@@ -3264,3 +3264,10 @@ vrsqrtph, 0x664e, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast
vrsqrtsh, 0x664f, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM }
// FP16 (HFNI) instructions end.
// PREFETCHI instructions.
prefetchit0, 0xf18, 0x7, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
prefetchit1, 0xf18, 0x6, CpuPREFETCHI|Cpu64, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex }
// PREFETCHI instructions end.
opcodes/i386-tbl.h
+3913 -3887
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File diff suppressed because it is too large Load Diff