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aarch64: Add the SME2 UNPK instructions

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This patch adds SUNPK and UUNPK, which unpack one register's
worth of elements to two registers' worth, or two registers'
worth to four registers' worth.
This commit is contained in:
Richard Sandiford
2023-03-30 11:09:16 +01:00
parent 6efa660124
commit fa64dc802c
9 changed files with 984 additions and 748 deletions
Download Patch File Download Diff File Expand all files Collapse all files
gas/testsuite/gas/aarch64/sme2-29-invalid.d
+3
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#as: -march=armv8-a
#source: sme2-29-invalid.s
#error_output: sme2-29-invalid.l
gas/testsuite/gas/aarch64/sme2-29-invalid.l
+39
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[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: expected '{' at operand 1 -- `sunpk 0,z0\.b'
[^ :]+:[0-9]+: Error: expected a register or register list at operand 2 -- `sunpk {z0\.h,z1\.h},0'
[^ :]+:[0-9]+: Error: missing braces at operand 1 -- `sunpk z0\.b,z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sunpk {z0\.b,z1\.b},z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sunpk {z0\.h-z1\.h}, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sunpk {z0\.s-z1\.s}, z0\.h
[^ :]+:[0-9]+: Info: sunpk {z0\.d-z1\.d}, z0\.s
[^ :]+:[0-9]+: Error: operand mismatch -- `sunpk {z0\.h,z1\.h},z0\.h'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sunpk {z0\.h-z1\.h}, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sunpk {z0\.s-z1\.s}, z0\.h
[^ :]+:[0-9]+: Info: sunpk {z0\.d-z1\.d}, z0\.s
[^ :]+:[0-9]+: Error: start register out of range at operand 1 -- `sunpk {z1\.h,z2\.h},z0\.b'
[^ :]+:[0-9]+: Error: operand mismatch -- `sunpk {z0\.b,z2\.b},z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sunpk {z0\.h, z2\.h}, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sunpk {z0\.s, z2\.s}, z0\.h
[^ :]+:[0-9]+: Info: sunpk {z0\.d, z2\.d}, z0\.s
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `sunpk {z1\.h-z3\.h},{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `sunpk {z2\.h-z4\.h},{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: expected a list of 4 registers at operand 1 -- `sunpk {z3\.h-z5\.h},{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: operand mismatch -- `sunpk {z0\.s-z3\.s},z0\.b'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sunpk {z0\.h-z3\.h}, z0\.b
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sunpk {z0\.s-z3\.s}, z0\.h
[^ :]+:[0-9]+: Info: sunpk {z0\.d-z3\.d}, z0\.s
[^ :]+:[0-9]+: Error: expected an SVE vector register at operand 2 -- `sunpk {z0\.s-z3\.s},{x0\.s-x1\.s}'
[^ :]+:[0-9]+: Error: operand mismatch -- `sunpk {z0\.s-z3\.s},{z0\.s-z3\.s}'
[^ :]+:[0-9]+: Info: did you mean this\?
[^ :]+:[0-9]+: Info: sunpk {z0\.s-z3\.s}, {z0\.h-z3\.h}
[^ :]+:[0-9]+: Info: other valid variant\(s\):
[^ :]+:[0-9]+: Info: sunpk {z0\.h-z3\.h}, {z0\.b-z3\.b}
[^ :]+:[0-9]+: Info: sunpk {z0\.d-z3\.d}, {z0\.s-z3\.s}
gas/testsuite/gas/aarch64/sme2-29-invalid.s
+14
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sunpk 0, z0.b
sunpk { z0.h, z1.h }, 0
sunpk z0.b, z0.b
sunpk { z0.b, z1.b }, z0.b
sunpk { z0.h, z1.h }, z0.h
sunpk { z1.h, z2.h }, z0.b
sunpk { z0.b, z2.b }, z0.b
sunpk { z1.h - z3.h }, { z0.b - z1.b }
sunpk { z2.h - z4.h }, { z0.b - z1.b }
sunpk { z3.h - z5.h }, { z0.b - z1.b }
sunpk { z0.s - z3.s }, z0.b
sunpk { z0.s - z3.s }, { x0.s - x1.s }
sunpk { z0.s - z3.s }, { z0.s - z3.s }
gas/testsuite/gas/aarch64/sme2-29-noarch.d
+3
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@@ -0,0 +1,3 @@
#as: -march=armv8-a+sme
#source: sme2-29.s
#error_output: sme2-29-noarch.l
gas/testsuite/gas/aarch64/sme2-29-noarch.l
+37
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[^ :]+: Assembler messages:
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.h,z1\.h},z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z30\.h,z31\.h},z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.h,z1\.h},z31\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.h-z3\.h},{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z28\.h-z31\.h},{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.h-z3\.h},{z30\.b-z31\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.s,z1\.s},z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z30\.s,z31\.s},z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.s,z1\.s},z31\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.s-z3\.s},{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z28\.s-z31\.s},{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.s-z3\.s},{z30\.h-z31\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.d,z1\.d},z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z30\.d,z31\.d},z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.d,z1\.d},z31\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.d-z3\.d},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z28\.d-z31\.d},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `sunpk {z0\.d-z3\.d},{z30\.s-z31\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.h,z1\.h},z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z30\.h,z31\.h},z0\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.h,z1\.h},z31\.b'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.h-z3\.h},{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z28\.h-z31\.h},{z0\.b-z1\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.h-z3\.h},{z30\.b-z31\.b}'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.s,z1\.s},z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z30\.s,z31\.s},z0\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.s,z1\.s},z31\.h'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.s-z3\.s},{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z28\.s-z31\.s},{z0\.h-z1\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.s-z3\.s},{z30\.h-z31\.h}'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.d,z1\.d},z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z30\.d,z31\.d},z0\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.d,z1\.d},z31\.s'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.d-z3\.d},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z28\.d-z31\.d},{z0\.s-z1\.s}'
[^ :]+:[0-9]+: Error: selected processor does not support `uunpk {z0\.d-z3\.d},{z30\.s-z31\.s}'
gas/testsuite/gas/aarch64/sme2-29.d
+45
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@@ -0,0 +1,45 @@
#as: -march=armv8-a+sme2
#objdump: -dr
[^:]+: file format .*
[^:]+:
[^:]+:
[^:]+: c165e000 sunpk {z0\.h-z1\.h}, z0\.b
[^:]+: c165e01e sunpk {z30\.h-z31\.h}, z0\.b
[^:]+: c165e3e0 sunpk {z0\.h-z1\.h}, z31\.b
[^:]+: c175e000 sunpk {z0\.h-z3\.h}, {z0\.b-z1\.b}
[^:]+: c175e01c sunpk {z28\.h-z31\.h}, {z0\.b-z1\.b}
[^:]+: c175e3c0 sunpk {z0\.h-z3\.h}, {z30\.b-z31\.b}
[^:]+: c1a5e000 sunpk {z0\.s-z1\.s}, z0\.h
[^:]+: c1a5e01e sunpk {z30\.s-z31\.s}, z0\.h
[^:]+: c1a5e3e0 sunpk {z0\.s-z1\.s}, z31\.h
[^:]+: c1b5e000 sunpk {z0\.s-z3\.s}, {z0\.h-z1\.h}
[^:]+: c1b5e01c sunpk {z28\.s-z31\.s}, {z0\.h-z1\.h}
[^:]+: c1b5e3c0 sunpk {z0\.s-z3\.s}, {z30\.h-z31\.h}
[^:]+: c1e5e000 sunpk {z0\.d-z1\.d}, z0\.s
[^:]+: c1e5e01e sunpk {z30\.d-z31\.d}, z0\.s
[^:]+: c1e5e3e0 sunpk {z0\.d-z1\.d}, z31\.s
[^:]+: c1f5e000 sunpk {z0\.d-z3\.d}, {z0\.s-z1\.s}
[^:]+: c1f5e01c sunpk {z28\.d-z31\.d}, {z0\.s-z1\.s}
[^:]+: c1f5e3c0 sunpk {z0\.d-z3\.d}, {z30\.s-z31\.s}
[^:]+: c165e001 uunpk {z0\.h-z1\.h}, z0\.b
[^:]+: c165e01f uunpk {z30\.h-z31\.h}, z0\.b
[^:]+: c165e3e1 uunpk {z0\.h-z1\.h}, z31\.b
[^:]+: c175e001 uunpk {z0\.h-z3\.h}, {z0\.b-z1\.b}
[^:]+: c175e01d uunpk {z28\.h-z31\.h}, {z0\.b-z1\.b}
[^:]+: c175e3c1 uunpk {z0\.h-z3\.h}, {z30\.b-z31\.b}
[^:]+: c1a5e001 uunpk {z0\.s-z1\.s}, z0\.h
[^:]+: c1a5e01f uunpk {z30\.s-z31\.s}, z0\.h
[^:]+: c1a5e3e1 uunpk {z0\.s-z1\.s}, z31\.h
[^:]+: c1b5e001 uunpk {z0\.s-z3\.s}, {z0\.h-z1\.h}
[^:]+: c1b5e01d uunpk {z28\.s-z31\.s}, {z0\.h-z1\.h}
[^:]+: c1b5e3c1 uunpk {z0\.s-z3\.s}, {z30\.h-z31\.h}
[^:]+: c1e5e001 uunpk {z0\.d-z1\.d}, z0\.s
[^:]+: c1e5e01f uunpk {z30\.d-z31\.d}, z0\.s
[^:]+: c1e5e3e1 uunpk {z0\.d-z1\.d}, z31\.s
[^:]+: c1f5e001 uunpk {z0\.d-z3\.d}, {z0\.s-z1\.s}
[^:]+: c1f5e01d uunpk {z28\.d-z31\.d}, {z0\.s-z1\.s}
[^:]+: c1f5e3c1 uunpk {z0\.d-z3\.d}, {z30\.s-z31\.s}
gas/testsuite/gas/aarch64/sme2-29.s
+47
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@@ -0,0 +1,47 @@
sunpk { z0.h, z1.h }, z0.b
sunpk { z30.h, z31.h }, z0.b
sunpk { z0.h, z1.h }, z31.b
sunpk { z0.h - z3.h }, { z0.b - z1.b }
sunpk { z28.h - z31.h }, { z0.b - z1.b }
sunpk { z0.h - z3.h }, { z30.b - z31.b }
sunpk { z0.s, z1.s }, z0.h
sunpk { z30.s, z31.s }, z0.h
sunpk { z0.s, z1.s }, z31.h
sunpk { z0.s - z3.s }, { z0.h - z1.h }
sunpk { z28.s - z31.s }, { z0.h - z1.h }
sunpk { z0.s - z3.s }, { z30.h - z31.h }
sunpk { z0.d, z1.d }, z0.s
sunpk { z30.d, z31.d }, z0.s
sunpk { z0.d, z1.d }, z31.s
sunpk { z0.d - z3.d }, { z0.s - z1.s }
sunpk { z28.d - z31.d }, { z0.s - z1.s }
sunpk { z0.d - z3.d }, { z30.s - z31.s }
uunpk { z0.h, z1.h }, z0.b
uunpk { z30.h, z31.h }, z0.b
uunpk { z0.h, z1.h }, z31.b
uunpk { z0.h - z3.h }, { z0.b - z1.b }
uunpk { z28.h - z31.h }, { z0.b - z1.b }
uunpk { z0.h - z3.h }, { z30.b - z31.b }
uunpk { z0.s, z1.s }, z0.h
uunpk { z30.s, z31.s }, z0.h
uunpk { z0.s, z1.s }, z31.h
uunpk { z0.s - z3.s }, { z0.h - z1.h }
uunpk { z28.s - z31.s }, { z0.h - z1.h }
uunpk { z0.s - z3.s }, { z30.h - z31.h }
uunpk { z0.d, z1.d }, z0.s
uunpk { z30.d, z31.d }, z0.s
uunpk { z0.d, z1.d }, z31.s
uunpk { z0.d - z3.d }, { z0.s - z1.s }
uunpk { z28.d - z31.d }, { z0.s - z1.s }
uunpk { z0.d - z3.d }, { z30.s - z31.s }
opcodes/aarch64-dis-2.c
+792 -748
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File diff suppressed because it is too large Load Diff
opcodes/aarch64-tbl.h
+4
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@@ -5722,6 +5722,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("sumlall", 0xc1108030, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zm_INDEX4_1), OP_SVE_SBB, F_OD (4), 0),
SME2_INSN ("sumlall", 0xc1200014, 0xfff09c1e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (2), 0),
SME2_INSN ("sumlall", 0xc1300014, 0xfff09c1e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SVE_ZnxN, SME_Zm), OP_SVE_SBB, F_OD (4), 0),
SME2_INSN ("sunpk", 0xc125e000, 0xff3ffc01, sme_size_22_hsd, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0),
SME2_INSN ("sunpk", 0xc135e000, 0xff3ffc23, sme_size_22_hsd, 0, OP2 (SME_Zdnx4, SME_Znx2), OP_SVE_VV_HSD_BHS, 0, 0),
SME2_INSN ("suvdot", 0xc1508038, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0),
SME2_INSN ("svdot", 0xc1500020, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
SME2_INSN ("svdot", 0xc1508020, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0),
@@ -5808,6 +5810,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME2_INSN ("usmlall", 0xc1a00004, 0xffe19c3e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx2, SME_Zmx2), OP_SVE_SBB, F_OD (2), 0),
SME2_INSN ("usmlall", 0xc1a10004, 0xffe39c7e, sme_misc, 0, OP3 (SME_ZA_array_off1x4, SME_Znx4, SME_Zmx4), OP_SVE_SBB, F_OD (4), 0),
SME2_INSN ("usvdot", 0xc1508028, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0),
SME2_INSN ("uunpk", 0xc125e001, 0xff3ffc01, sme_size_22_hsd, 0, OP2 (SME_Zdnx2, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0),
SME2_INSN ("uunpk", 0xc135e001, 0xff3ffc23, sme_size_22_hsd, 0, OP2 (SME_Zdnx4, SME_Znx2), OP_SVE_VV_HSD_BHS, 0, 0),
SME2_INSN ("uvdot", 0xc1500030, 0xfff09038, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx2, SME_Zm_INDEX2), OP_SVE_SHH, F_OD (2), 0),
SME2_INSN ("uvdot", 0xc1508030, 0xfff09078, sme_misc, 0, OP3 (SME_ZA_array_off3_0, SME_Znx4, SME_Zm_INDEX2), OP_SVE_SBB, F_OD (4), 0),
SME2_INSN ("whilege", 0x25204010, 0xff20dc18, sme_size_22, 0, OP4 (SME_PNd3, Rn, Rm, SME_VLxN_13), OP_SVE_VXXU_BHSD, 0, 0),