8375 Commits

Author SHA1 Message Date
Jan Beulich
32546502f3 x86: use local variable in check_VecOperands()
This is just to make a subsequent change a little easier to read.
2018-03-22 08:47:16 +01:00
Jan Beulich
1212781b35 ix86: allow HLE store of accumulator to absolute address
Since they're shorter to encode, the 0xa0...0xa3 encodings are preferred
for moves between accumulator and absolute address outside of 64-bit
mode. With HLE release semantics this encoding is unsupported though,
with the assembler raising an error. The operation is valid though, we
merely need to pick the longer encoding in that case.
2018-03-22 08:33:38 +01:00
Jan Beulich
9f79e88693 x86: fix swapped operand handling for BNDMOV
The wrong placement of the Load attribute in the templates prevented
this from working. The disassembler also didn't handle this consistently
with other similar dual-encoding insns.
2018-03-22 08:32:50 +01:00
Jan Beulich
d6793fa1ac x86/Intel: fix fallout from earlier template folding
While many templates allowing multiple suitably matching XMM/YMM/ZMM
operand sizes can be folded, a few need to be split in order to not
wrongly accept "xmmword ptr" operands when only XMM registers are
permitted (and memory operands are more narrow). Add a test case
validating this.
2018-03-22 08:31:43 +01:00
Jan Beulich
f776822506 x86: fold a few XOP templates
Also add a new test case verifying that mixed operands of SIMD insns
with a size-less memory operand in the middle are properly rejected.
2018-03-22 08:29:45 +01:00
Nick Clifton
315aa1cf83 Updated Spanish translation for the bfd/ sub-directory, and updated Ukranian translation for the gas/ sub-directory.
bfd	* po/es.po: Updated Spanish translation.
gas	* po/uk.po: Updated Ukranian translation.
2018-03-19 10:49:13 +00:00
Jim Wilson
ca2fd32c55 RISC-V: Emit better warning for unknown CSR.
gas/
	* config/tc-riscv.c (check_absolute_expr): Expand comment.  New
	parameter maybe_csr.  If maybe_csr and O_symbol, print CSR name.
	(riscv_ip): Add new argument to check_absolute_expr calls.
	* testsuite/gas/riscv/bad-csr.d: New.
	* testsuite/gas/riscv/bad-csr.l: New.
	* testsuite/gas/riscv/bad-csr.s: New.
2018-03-16 10:03:57 -07:00
Jim Wilson
399912428d Missing testcase files for last commit. 2018-03-14 16:05:44 -07:00
Jim Wilson
0e35537d75 RISC-V: Add .insn support.
gas/ChangeLog
	2018-03-07  Kito Cheng  <kito.cheng@gmail.com>
	* config/tc-riscv.c (opcode_name_list): New.
	(opcode_names_hash): Likewise.
	(init_opcode_names_hash): Likewise.
	(opcode_name_lookup): Likewise.
	(validate_riscv_insn): New argument length, and add new format
	which used in .insn directive.
	(md_begin): Refine hash table initialization logic into
	init_opcode_hash.
	(init_opcode_hash): New.
	(my_getOpcodeExpression): Parse opcode name for .insn.
	(riscv_ip): New argument hash, able to handle .insn directive.
	(s_riscv_insn): Handler for .insn directive.
	(riscv_pseudo_table): New entry for .insn.
	* doc/c-riscv.texi: Add documentation for .insn directive.
	* testsuite/gas/riscv/insn.d: Add testcase for .insn directive.
	* testsuite/gas/riscv/insn.s: Likewise.

	include/ChangeLog
	2018-03-07  Kito Cheng  <kito.cheng@gmail.com>
	* opcode/riscv.h (OP_MASK_FUNCT3): New.
	(OP_SH_FUNCT3): Likewise.
	(OP_MASK_FUNCT7): Likewise.
	(OP_SH_FUNCT7): Likewise.
	(OP_MASK_OP2): Likewise.
	(OP_SH_OP2): Likewise.
	(OP_MASK_CFUNCT4): Likewise.
	(OP_SH_CFUNCT4): Likewise.
	(OP_MASK_CFUNCT3): Likewise.
	(OP_SH_CFUNCT3): Likewise.
	(riscv_insn_types): Likewise.

	opcodes/ChangeLog
	2018-03-07  Kito Cheng  <kito.cheng@gmail.com>
	* riscv-opc.c (riscv_insn_types): New.
2018-03-14 16:04:03 -07:00
Nick Clifton
b4a3689a68 Updated Russian and Brazilian Portuguese translations.
ld	* po/pt_BR.po: Updated Brazilian Portuguese translation.
opcodes	* po/pt_BR.po: Updated Brazilian Portuguese translation.
gas	* po/ru.po: Updated Russian translation.
2018-03-13 16:57:29 +00:00
H.J. Lu
80c34c3812 x86: Encode EVEX instructions with VEX128 if possible
If EVEX encoding isn't required, we can encode EVEX instructions with
VEX128.

	* config/tc-i386.c (optimize_encoding): Encode EVEX instructions
	with VEX128 if EVEX encoding isn't required.
	* testsuite/gas/i386/optimize-1.d: Updated.
	* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
2018-03-09 08:10:40 -08:00
H.J. Lu
0ba3a73180 x86: Strip whitespace in check_VecOperations
Since the addition of pseudo prefixes changed how the scrubber treats
'{', we need to explicitly strip whitespace in check_VecOperations ().

	* config/tc-i386.c (check_VecOperations): Strip whitespace.
	* testsuite/gas/i386/optimize-1.s: Add whitespaces before
	{%k7} and {z},
	* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
2018-03-09 03:51:31 -08:00
H.J. Lu
0089daceab x86: Optimize with EVEX128 encoding for AVX512VL
We can optimize AVX512 instructions with EVEX128 only if AVX512VL is
enabled:

1. Instruction is an AVX512VL instruction. Or
2. AVX512VL is enabled explicitly by -march=+avx512vl/".arch .avx512vl".

We should optimize EVEX instructions with EVEX128 encoding when pseudo
{evex} prefix is used.

	* config/tc-i386.c (set_cpu_arch): Set cpu_arch_isa_flags.
	(md_parse_option): Likewise.
	(optimize_encoding): Check i.tm.cpu_flags and cpu_arch_isa_flags
	for cpuavx512vl instead of cpu_arch_flags.  Optimize EVEX with
	EVEX128 when EVEX encoding is required.
	* testsuite/gas/i386/i386.exp: Run optimize-4, optimize-5,
	x86-64-optimize-5 and x86-64-optimize-6.
	* testsuite/gas/i386/optimize-1.d: Updated.
	* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
	* testsuite/gas/i386/optimize-4.d: New file.
	* testsuite/gas/i386/optimize-4.s: Likewise.
	* testsuite/gas/i386/optimize-5.d: Likewise.
	* testsuite/gas/i386/optimize-5.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-5.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-5.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-6.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-6.s: Likewise.
2018-03-08 19:57:48 -08:00
H.J. Lu
d3d50934a9 x86-64: Also optimize "clr reg64"
"clr reg" is an alias of "xor reg, reg".  We can encode "clr reg64" as
"xor reg32, reg32".

gas/

	* config/tc-i386.c (optimize_encoding): Also encode "clr reg64"
	as "xor reg32, reg32".
	* testsuite/gas/i386/x86-64-optimize-1.s: Add "clr reg64" tests.
	* testsuite/gas/i386/x86-64-optimize-1.d: Updated.

opcodes/

	* i386-opc.tbl: Add Optimize to clr.
	* i386-tbl.h: Regenerated.
2018-03-08 06:41:34 -08:00
H.J. Lu
bd5dea8822 x86: Remove support for old (<= 2.8.1) versions of gcc
Old (<= 2.8.1) versions of gcc generate broken fsubp, fsubrp, fdivp and
fdivrp instructions.  Assembler translates them to correct ones with a
warning:

[hjl@gnu-cfl-1 gas]$ cat x.s
	fsubp %st(3),%st
[hjl@gnu-cfl-1 gas]$ gcc -c x.s
x.s: Assembler messages:
x.s:1: Warning: translating to `fsubp %st,%st(3)'
[hjl@gnu-cfl-1 gas]$

This patch removes support for old (<= 2.8.1) versions of gcc:

[hjl@gnu-cfl-1 gas]$ ./as-new -o x.o x.s
x.s: Assembler messages:
x.s:1: Error: operand type mismatch for `fsubp'
[hjl@gnu-cfl-1 gas]$

gas/

	* NEWS: Mention -mold-gcc removal.
	* config/tc-i386.c (i386_error): Remove old_gcc_only.
	(old_gcc): Removed.
	(match_template): Remove old gcc support.
	(OPTION_MOLD_GCC): Removed.
	(OPTION_MRELAX_RELOCATIONS): Updated.
	(md_longopts): Remove OPTION_MOLD_GCC.
	(md_parse_option): Likewise.
	(md_show_usage): Remove -mold-gcc.
	* testsuite/gas/i386/general.s: Convert fsub/fdiv tests for old
	(<= 2.8.1) versions of gcc.
	* testsuite/gas/i386/intel.s: Likewise.
	* testsuite/gas/i386/general.l: Updated.
	* testsuite/gas/i386/intel-intel.d: Likewise.
	* testsuite/gas/i386/intel.d: Likewise.
	* testsuite/gas/i386/intel.e: Likewise.
	* testsuite/gas/i386/i386.exp: Don't pass -mold-gcc to general.

include/

	* opcode/i386 (OLDGCC_COMPAT): Removed.

opcodes/

	* i386-gen.c (opcode_modifiers): Remove OldGcc.
	* i386-opc.h (OldGcc): Removed.
	(i386_opcode_modifier): Remove oldgcc.
	* i386-opc.tbl: Remove fsubp, fsubrp, fdivp and fdivrp
	instructions for old (<= 2.8.1) versions of gcc.
	* i386-tbl.h: Regenerated.
2018-03-08 06:31:52 -08:00
Jan Beulich
e771e7c9fb x86: fold several AVX512VL templates
The differences between some of the register and memory forms of the
same insn often don't really require the templates to be separate. For
example, Disp8MemShift is simply irrelevant to register forms. Fold
these as far as possible, and also fold register-only forms. Further
folding is possible, but needs other prereq work done first.

A note regarding EVEXDYN: This is intended to be used only when no other
properties of the template would make is_evex_encoding() return true. In
all "normal" cases I think it is preferable to omit this indicator, to
keep the table half way readable.
2018-03-08 08:58:55 +01:00
Jan Beulich
ed438a93f1 x86: fold certain AVX512 rotate and shift templates
Their memory forms were bogusly using VexLWP instead of VexNDD. Adjust
VexNDD handling to cope with these, allowing their register and memory
forms to be folded.
2018-03-08 08:58:05 +01:00
Jan Beulich
d2224064f1 x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIX
They aren't really useful (anymore?): The conflicting operand size check
isn't applicable to any insn validly using respective memory operand
sizes (and if they're used wrongly, another error would result), and the
logic in process_suffix() can be easily changed to work without them.

While re-structuring conditionals in process_suffix() also drop the
CMPXCHG8B special case in favor of a NoRex64 attribute in the opcode
table.
2018-03-08 08:52:27 +01:00
Jan Beulich
23e42951f2 x86: correct operand size match checks for BMI/BMI2 insns
Some BMI/BMI2 insns allow their middle operands to be a memory one. In
such a case, matching register types between operands 0 and 1 as well as
1 and 2 won't help - operands 0 and 2 also need to be checked.
2018-03-08 08:51:18 +01:00
Jan Beulich
8819ada6c4 x86: fold redundant expressions in process_suffix()
There's no point repeatedly evaluating i.types[op].bitfield.reg.
2018-03-08 08:50:13 +01:00
Jan Beulich
548d0ee6e7 x86: simplify result processing of cpu_flags_match()
Make more obvious what the success and failure paths are, and in
particular that what used to be at the "skip" label can't be reached
by what used to be straight line code.
2018-03-08 08:48:10 +01:00
Jan Beulich
929f69fa96 x86: add GFNI, VAES, and VPCLMUL checking to cpu_flags_match()
Just like for the AVX/AES and AVX/PCLMUL combinations, AVX/GFN,
AVX512F/GFNI, AVX512F/VAES, and AVX512F/PCLMUL need special handling to
deal with the pair of required checks specified in the templates.
2018-03-08 08:47:32 +01:00
Jan Beulich
ab592e757e x86: change AVX512VL handling in cpu_flags_match()
In order to add an AVX512F counterpart to the present AVX checking, it
is better to move the AVX512VL check out of the conditional it's
currently in.
2018-03-08 08:45:56 +01:00
Jan Beulich
db12e14ea0 x86: drop CPU_FLAGS_32BIT_MATCH
It has become a plain alias of CPU_FLAGS_ARCH_MATCH now.
2018-03-08 08:45:25 +01:00
Jan Beulich
b9d498173c x86: simplify AVX checks in cpu_flags_match()
No caller cares about the specifics of CPU_FLAGS_{AES,AVX,PCLMUL}_MATCH,
so drop those and fold the nested if()-s.
2018-03-08 08:44:52 +01:00
Jan Beulich
bcb1753ee6 x86: avoid cpu_flags_match() bogusly setting CPU_FLAGS_ARCH_MATCH 2018-03-08 08:44:12 +01:00
Jan Beulich
6e3e5c9e41 x86: extend SSE check to PCLMULQDQ, AES, and GFNI insns
When aiming at not mixing SSE and AVX insns, these should be warned
about the same way other non-AVX ones are treated.
2018-03-08 08:35:01 +01:00
Jan Beulich
38e314eb06 x86: drop FloatD
It can be expressed by D, when making the consumer look at operand size
to tell apart both uses.
2018-03-08 08:34:09 +01:00
Jan Beulich
d53e6b98a2 x86/Intel: correct disassembly of fsub*/fdiv*
fsub/fsubr/fsubp/fsubrp as well as fdiv/fdivr/fdivp/fdivrp disassembly
should match (a) the Intel SDM and (b) respective input fed to gas (both
of course with the exception of when we intentionally convert bogus
insns, accompanied by a warning).
2018-03-08 08:33:06 +01:00
Jan Beulich
a477a8c4f4 x86: adjust 4-XMM-register-group related warning
Drop "second": For one there's no other source register (the other
source operand is in memory), and in Intel syntax such numbering would
also be wrong.

Take the opportunity and also
- properly place declarations ahead of statements
- use %u format for unsigned int arguments
- fix indentation
2018-03-08 08:27:28 +01:00
Jan Beulich
2907c2f555 x86: bogus VMOVD with 64-bit operands should only allow for registers
These templates exist solely to satisfy gcc's needs, and gcc only
produces these with register operands.
2018-03-08 08:26:35 +01:00
Jan Beulich
73053c1fc4 x86: fold AVX vcvtpd2ps memory forms
This requires a change to ModR/M handling: Recording of displacement
types must not discard operand size information. Change the respective
code to alter only .disp<N>.
2018-03-08 08:25:31 +01:00
Alan Modra
6a7524c6aa Really remove unnecessary power9 group terminating nop
Oops, not tested well enough.  -mpower9 sets all the PPC_OPCODE_POWERn
for n <= 9.

	* config/tc-ppc.c (ppc_handle_align): Correct last patch.  Really
	don't emit a group terminating nop for power9.  Simplify cpu
	tests.
2018-03-08 14:37:26 +10:30
Alan Modra
3fea0c3b3f Remove unnecessary power9 group terminating nop
Power9 doesn't have a group terminating nop, so we may as well emit a
normal nop for power9.  Not that it matters a great deal, I believe
ori 2,2,0 will be treated exactly as ori 0,0,0 by the hardware.

	* config/tc-ppc.c (ppc_handle_align): Don't emit a group
	terminating nop for power9.
2018-03-08 14:17:01 +10:30
H.J. Lu
3ae729d5a4 x86: Rewrite NOP generation for fill and alignment
Rewrite NOP generation for fill and code alignment by:

1. Add a 11-byte NOP with another 0x66 prefix.
2. Remove the multi-byte NOP entries which consist of 2 instructions.
3. Select proper NOPs based on ISA and processor tuning.
4. Generate multiple NOPs with the longer NOPs first followed by the
shorter NOP.
5. Use jump for larger NOP padding:
   a. > 8 bytes (2 NOPs) in 16-bit mode.
   b. > 14 bytes (2 NOPs) for older processors.
   c. > 77 bytes (7 NOPs) for newer processors.
6. Update MAX_MEM_FOR_RS_ALIGN_CODE to 4095.

	PR gas/22874
	* config/tc-i386.c (f32_5): Removed.
	(f32_8): Likewise.
	(f32_9): Likewise.
	(f32_10): Likewise.
	(f32_11): Likewise.
	(f32_12): Likewise.
	(f32_13): Likewise.
	(f32_14): Likewise.
	(f16_5): Likewise.
	(f16_6): Likewise.
	(f16_7): Likewise.
	(f16_8): Likewise.
	(jump_31): Likewise.
	(alt64_11): Likewise.
	(alt64_patt): Likewise.
	(jump_disp8): New.
	(jump32_disp32): Likewise.
	(jump16_disp32): Likewise.
	(alt_11): Likewise.
	(f32_patt): Updated.
	(f16_patt): Likewise.
	(alt_patt): Add alt_11.
	(i386_align_code): Merged with ...
	(i386_generate_nops): This.  Rewritten.
	(fits_in_imm7): Moved before i386_generate_nops.
	(fits_in_imm31): Likewise.
	* config/tc-i386.h (MAX_MEM_FOR_RS_ALIGN_CODE): Updated to
	4095.
	(i386_align_code): Removed.
	(HANDLE_ALIGN): Rewritten with i386_generate_nops.
	* doc/as.texinfo: Update limits of control byte for x86 .nops
	directive.
	* testsuite/gas/i386/i386.exp: Run nops-7 and x86-64-nops-7.
	* gas/testsuite/gas/i386/noavx-3.l: Updated.
	* gas/testsuite/gas/i386/nop-1.d: Likewise.
	* gas/testsuite/gas/i386/nop-1.s: Likewise.
	* gas/testsuite/gas/i386/nop-2.d: Likewise.
	* gas/testsuite/gas/i386/nop-2.s: Likewise.
	* gas/testsuite/gas/i386/nop-3.d: Likewise.
	* gas/testsuite/gas/i386/nop-4.d: Likewise.
	* gas/testsuite/gas/i386/nop-5.d: Likewise.
	* gas/testsuite/gas/i386/nop-5.s: Likewise.
	* gas/testsuite/gas/i386/nop-6.d: Likewise.
	* gas/testsuite/gas/i386/nop-bad-1.l: Likewise.
	* gas/testsuite/gas/i386/nops-1-core2.d: Likewise.
	* gas/testsuite/gas/i386/nops-1-i386-i686.d: Likewise.
	* gas/testsuite/gas/i386/nops-1-i386.d: Likewise.
	* gas/testsuite/gas/i386/nops-1-i686.d: Likewise.
	* gas/testsuite/gas/i386/nops-1-k8.d: Likewise.
	* gas/testsuite/gas/i386/nops-1.d: Likewise.
	* gas/testsuite/gas/i386/nops-2-core2.d: Likewise.
	* gas/testsuite/gas/i386/nops-2-i386.d: Likewise.
	* gas/testsuite/gas/i386/nops-2.d: Likewise.
	* gas/testsuite/gas/i386/nops-3-i386.d: Likewise.
	* gas/testsuite/gas/i386/nops-3-i686.d: Likewise.
	* gas/testsuite/gas/i386/nops-3.d: Likewise.
	* gas/testsuite/gas/i386/nops-4-i386.d: Likewise.
	* gas/testsuite/gas/i386/nops-4-i686.d: Likewise.
	* gas/testsuite/gas/i386/nops-4.d: Likewise.
	* gas/testsuite/gas/i386/nops-4a-i686.d: Likewise.
	* gas/testsuite/gas/i386/nops-5-i686.d: Likewise.
	* gas/testsuite/gas/i386/nops-5.d: Likewise.
	* gas/testsuite/gas/i386/nops-6.d: Likewise.
	* gas/testsuite/gas/i386/nops16-1.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nop-1.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nop-2.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nop-5.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-1-core2.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-1-g64.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-1-k8.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-1-pentium.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-1.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-2.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-3.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-4-core2.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-4-k8.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-4.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-5-k8.d: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-5.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-1-core2.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-1-k8.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-1-pentium.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-1.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-2.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-3.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-4-core2.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-4-k8.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-4.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-5-k8.d: Likewise.
	* gas/testsuite/gas/i386/ilp32/x86-64-nops-5.d: Likewise.
	* gas/testsuite/gas/i386/nops-7.d: New file.
	* gas/testsuite/gas/i386/nops-7.s: Likewise.
	* gas/testsuite/gas/i386/x86-64-nops-7.d: Likewise.
2018-03-07 04:18:56 -08:00
Alan Modra
52fe4420b7 XCOFF disassembler
xcoff (32-bit) objdump accepted but ignored -M options unless
-mpowerpc was also given.  This patch fixes that, leaving the default
as -Mpwr for xcoff.  I've also enabled more tests for xcoff targets.

binutils/
	* configure.ac: Add objdump_private_desc_xcoff for rs6000.
	* configure: Regenerate.
gas/
	* testsuite/gas/ppc/aix.exp: Run for rs6000 too.
	* testsuite/gas/ppc/ppc.exp: Run more tests for non-ELF targets.
	* testsuite/gas/ppc/machine.d: Don't run for PE targets.
opcodes/
	* disassemble.c (disassembler): Use bfd_arch_powerpc entry for
	bfd_arch_rs6000.
	* disassemble.h (print_insn_rs6000): Delete.
	* ppc-dis.c (powerpc_init_dialect): Handle rs6000.
	(disassemble_init_powerpc): Call powerpc_init_dialect for rs6000.
	(print_insn_rs6000): Delete.
2018-03-07 16:56:39 +10:30
Thomas Preud'homme
e7da50fa4b [ARM] Fix NULL dereference of march_ext_opt
Commit 4d354d8b8932d450c77fd52f3501662827523014 introduced a NULL
pointer dereference by replacing a pointer assignment by a pointer
dereference assignment without adding a NULL pointer check. This patch
fixes it.

2018-03-02  Thomas Preud'homme  <thomas.preudhomme@arm.com>

gas/
	* config/tc-arm.c (md_begin): Add NULL pointer check before
	dereferencing march_ext_opt.
2018-03-02 10:47:14 +00:00
Thomas Preud'homme
4d354d8b89 [ARM] Clean up selection of feature bits
I've always found the code in ARM backend of gas to control what
CPU/architecture and FPU are selected by the user and to support
autodetection of features complex and confusing. Chief among the
issues I have with that code is the lack of comments to explain
the meaning of the various variables. This patch addresses that
and much more:

- add comments to explain meaning of all arm_feature_set variables
- keep track of currently selected CPU, extensions and FPU in a separate
  set of new variables
- make naming of variable more consistent
- remove dead code
- simplify handling of extensions

The overall approach is as follows:

* restrict m*_opt variable to hold the feature bits of the
  corresponding mcpu/march/mfpu command-line options
* record selected CPU, extensions and FPU in new selected_* during
  md_begin
* whenever a .cpu/.arch/.arch_extension/.fpu directive is met, update
  the corresponding selected_* variables (eg. selected_arch, then
  selected_cpu for a .cpu or .arch directive) and then finally
  cpu_variant from them
* pass extension feature set pointer by value to arm_parse_extension
  since it's only ever called from arm_parse_cpu and arm_parse_arch
  which allocate the extension feature set themselves
* likewise, remove allocation from s_arm_arch_extension since the use
  of arm_feature_set structure for selected_ext rather than a pointer
  alleviate the need for it
* in autodetection mode, only set all CPU fits in cpu_variant but leave
  selected_cpu* variables unset
* in md_begin, remove dead "else if" to set a default FPU when no FPU
  was selected. Setting a default FPU based on CPU as did the code
  before it turn dead should be based on the default FPU field of the
  CPU and architecture table as will be done in a separate patch. Logic
  is wrong anyway since it sets VFP2 as default FPU for Armv6-M and
  Armv7-M

Hopefully that should be enough to understand the change but if not feel
free to ask questions about the patch. While I believe the new code is
easier to understand, it remains complex and the old one was even more
complex so the change is difficult to understand.

2018-03-01  Thomas Preud'homme  <thomas.preudhomme@arm.com>

	gas/
	* config/tc-arm.c (cpu_variant, arm_arch_used, thumb_arch_used,
	legacy_cpu, legacy_fpu, mcpu_cpu_opt, dyn_mcpu_ext_opt,
	mcpu_fpu_opt, march_cpu_opt, dyn_march_ext_opt, march_fpu_opt,
	mfpu_opt, object_arch, selected_cpu): Comment meaning of variables.
	(dyn_mcpu_ext_opt): Also rename into ...
	(mcpu_ext_opt): This.
	(dyn_march_ext_opt): Also rename into ...
	(march_ext_opt): This.
	(object_arch): Also rename into ...
	(selected_object_arch): This and make it a plain arm_feature_set
	structure.
	(selected_arch, selected_ext, selected_fpu): New static variables.
	(mark_feature_used): Fix comments, feature is marked as used iff it is
	currently allowed.
	(do_bx): Adapt to change in name and type of object_arch.
	(md_begin): Set selected_arch rather than mcpu_cpu_opt, selected_ext
	rather than dyn_mcpu_ext_opt and selected_fpu rather than mfpu_opt.
	Remove dead code to set default FPU if architecture version is greater
	than 5.  Set all CPU bits of cpu_variant directly in autodection
	leaving mcpu_cpu_opt, selected_arch and selected_cpu unset.
	(arm_parse_extension): Take extension feature set pointer parameter by
	value rather than by pointer.  Remove allocation code.  Adapt code
	accordingly.
	(arm_parse_cpu): Adapt to variable renaming and changes in
	arm_parse_extension () signature.
	(arm_parse_arch): Likewise.
	(aeabi_set_public_attributes): Also set selected_arch and selected_ext
	in addition to selected_cpu.  Set flags_arch and flags_ext from them
	instead of selected_cpu.  Adapt to variables renaming and type change.
	(arm_md_post_relax): Adapt to variable renaming.
	(s_arm_cpu): Set selcted_cpu_cpu and selected_ext instead of
	mcpu_cpu_opt and dyn_mcpu_ext_opt.  Set selected_cpu from them and
	cpu_variant from selected_cpu and selected_fpu.
	(s_arm_arch): Likewise.
	(s_arm_object_arch): Adapt to variable renaming.
	(s_arm_arch_extension): Use ARM_CPU_IS_ANY instead of checking feature
	set against arm_any.  Check selected_arch rather than *mcpu_cpu_opt.
	Set selected_ext rather than *dyn_mcpu_ext_opt and remove allocation
	code.
	(s_arm_fpu): Set selected_fpu instead of mfpu_opt.  Set all CPU feature
	bits if in autodetection mode.
2018-03-01 16:23:38 +00:00
H.J. Lu
8305403a1f x86: Encode AVX256/AVX512 vpsub[bwdq] with VEX128/EVEX128
When 2 source registers are identical, AVX256 and AVX512 vpsub[bwdq]
instructions can be encoded with VEX128 or EVEX128 encodings.

gas/

	* config/tc-i386.c (optimize_encoding): Optimize AVX256 and
	AVX512 vpsub[bwdq] instructions.
	* testsuite/gas/i386/optimize-1.s: Add tests for AVX256 and
	AVX512 vpsub[bwdq] instructions.
	* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
	* testsuite/gas/i386/optimize-1.d: Updated.
	* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.

opcodes/

	* * i386-opc.tbl: Add "Optimize" to AVX256 and AVX512
	vpsub[bwdq] instructions.
	* i386-tbl.h: Regenerated.
2018-03-01 06:08:31 -08:00
Alan Modra
e184813fdb Add missing translations to ALL_LINGUAS
binutils/
	* configure.ac (ALL_LINGUAS): Add sr.  Sort.
	* configure: Regenerate.
gas/
	* configure.ac (ALL_LINGUAS): Add uk.  Sort.
	* configure: Regenerate.
gprof/
	* configure.ac (ALL_LINGUAS): Add it, ro, ru, uk.  Sort.
	* configure: Regenerate.
ld/
	* configure.ac (ALL_LINGUAS): Add ja.  Sort.
	* configure: Regenerate.
opcodes/
	* configure.ac (ALL_LINGUAS): Sort.
	* configure: Regenerate.
2018-03-01 09:17:02 +10:30
H.J. Lu
8f065d3b4a gas: Rename .nop directive to .nops
Since directives of NO_PSEUDO_DOT targets don't have the leading '.'
and "nop" can be a valid instruction, rename .nop directive to .nops
to avoid conflict.

	* NEWS: Rename .nop to .nops.
	* doc/as.texinfo: Likewise.
	* read.c (potable): Add "nops".  Remove "nop".
	(s_nop): Renamed to ...
	(s_nops): This.
	* read.h (s_nop): Renamed to ...
	(s_nops): This.
	* write.c (cvt_frag_to_fill): Rename .nop to .nops.
	(md_generate_nops): Likewise.
	(relax_segment): Likewise.
	* testsuite/gas/i386/nop-1.d: Updated.
	* testsuite/gas/i386/nop-1.s: Likewise.
	* testsuite/gas/i386/nop-2.d: Likewise.
	* testsuite/gas/i386/nop-2.s: Likewise.
	* testsuite/gas/i386/nop-3.d: Likewise.
	* testsuite/gas/i386/nop-3.s: Likewise.
	* testsuite/gas/i386/nop-4.d: Likewise.
	* testsuite/gas/i386/nop-4.s: Likewise.
	* testsuite/gas/i386/nop-5.d: Likewise.
	* testsuite/gas/i386/nop-5.s: Likewise.
	* testsuite/gas/i386/nop-6.d: Likewise.
	* testsuite/gas/i386/nop-6.s: Likewise.
	* testsuite/gas/i386/nop-bad-1.l: Likewise.
	* testsuite/gas/i386/nop-bad-1.s: Likewise.
	* testsuite/gas/i386/x86-64-nop-1.d: Likewise.
	* testsuite/gas/i386/x86-64-nop-2.d: Likewise.
	* testsuite/gas/i386/x86-64-nop-3.d: Likewise.
	* testsuite/gas/i386/x86-64-nop-4.d: Likewise.
	* testsuite/gas/i386/x86-64-nop-5.d: Likewise.
	* testsuite/gas/i386/x86-64-nop-6.d: Likewise.
2018-02-27 14:46:03 -08:00
H.J. Lu
b6f8c7c452 x86: Add -O[2|s] assembler command-line options
On x86, some instructions have alternate shorter encodings:

1. When the upper 32 bits of destination registers of

andq $imm31, %r64
testq $imm31, %r64
xorq %r64, %r64
subq %r64, %r64

known to be zero, we can encode them without the REX_W bit:

andl $imm31, %r32
testl $imm31, %r32
xorl %r32, %r32
subl %r32, %r32

This optimization is enabled with -O, -O2 and -Os.
2. Since 0xb0 mov with 32-bit destination registers zero-extends 32-bit
immediate to 64-bit destination register, we can use it to encode 64-bit
mov with 32-bit immediates.  This optimization is enabled with -O, -O2
and -Os.
3. Since the upper bits of destination registers of VEX128 and EVEX128
instructions are extended to zero, if all bits of destination registers
of AVX256 or AVX512 instructions are zero, we can use VEX128 or EVEX128
encoding to encode AVX256 or AVX512 instructions.  When 2 source
registers are identical, AVX256 and AVX512 andn and xor instructions:

VOP %reg, %reg, %dest_reg

can be encoded with

VOP128 %reg, %reg, %dest_reg

This optimization is enabled with -O2 and -Os.
4. 16-bit, 32-bit and 64-bit register tests with immediate may be
encoded as 8-bit register test with immediate.  This optimization is
enabled with -Os.

This patch does:

1. Add {nooptimize} pseudo prefix to disable instruction size
optimization.
2. Add optimize to i386_opcode_modifier to tell assembler that encoding
of an instruction may be optimized.

gas/

	PR gas/22871
	* NEWS: Mention -O[2|s].
	* config/tc-i386.c (_i386_insn): Add no_optimize.
	(optimize): New.
	(optimize_for_space): Likewise.
	(fits_in_imm7): New function.
	(fits_in_imm31): Likewise.
	(optimize_encoding): Likewise.
	(md_assemble): Call optimize_encoding to optimize encoding.
	(parse_insn): Handle {nooptimize}.
	(md_shortopts): Append "O::".
	(md_parse_option): Handle -On.
	* doc/c-i386.texi: Document -O0, -O, -O1, -O2 and -Os as well
	as {nooptimize}.
	* testsuite/gas/cfi/cfi-x86_64.d: Pass -O0 to assembler.
	* testsuite/gas/i386/ilp32/cfi/cfi-x86_64.d: Likewise.
	* testsuite/gas/i386/i386.exp: Run optimize-1, optimize-2,
	optimize-3, x86-64-optimize-1, x86-64-optimize-2,
	x86-64-optimize-3 and x86-64-optimize-4.
	* testsuite/gas/i386/optimize-1.d: New file.
	* testsuite/gas/i386/optimize-1.s: Likewise.
	* testsuite/gas/i386/optimize-2.d: Likewise.
	* testsuite/gas/i386/optimize-2.s: Likewise.
	* testsuite/gas/i386/optimize-3.d: Likewise.
	* testsuite/gas/i386/optimize-3.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-1.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-1.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-2.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-2.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-3.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-3.s: Likewise.
	* testsuite/gas/i386/x86-64-optimize-4.d: Likewise.
	* testsuite/gas/i386/x86-64-optimize-4.s: Likewise.

opcodes/

	PR gas/22871
	* i386-gen.c (opcode_modifiers): Add Optimize.
	* i386-opc.h (Optimize): New enum.
	(i386_opcode_modifier): Add optimize.
	* i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
	"sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
	"and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
	"movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
	vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
	vpxord and vpxorq.
	* i386-tbl.h: Regenerated.
2018-02-27 07:36:43 -08:00
Nick Clifton
bc7c0509f2 Add a new Portuguese translation for the binutils sub-directory, and update the Russian translation for the gas sub-directory.
gas	* po/ru.po: Updated Russian translation.

binutils* po/pt.po: New Portuguese translation.
	* configure.ac (ALL_LINGUAS): Add pt.
	* configure: Regenerate.
2018-02-27 12:27:30 +00:00
Maciej W. Rozycki
d7c798565e GAS/doc: Clean up .dc' and .ds' directive descriptions
gas/
	* doc/as.texinfo (Pseudo Ops): Clean up `.dc' and `.ds'
	descriptions.
2018-02-26 16:11:03 +00:00
Nick Clifton
46c685acda Fix typo in documentation of assembler's .dc directive.
* doc/as.texinfo (Dc): Fix typo.
2018-02-26 11:28:23 +00:00
Alan Modra
6e05870c97 BFD messages
bfd/
	* archive.c, * bfd.c, * linker.c, * reloc.c, * stabs.c,
	* syms.c: Standardize error/warning messages.
binutils/
	* testsuite/binutils-all/mips/mips-reginfo-n32.d,
	* testsuite/binutils-all/mips/mips-reginfo.d: Update.
gas/
	* testsuite/gas/mips/reginfo-2.l: Update.
ld/
	* testsuite/ld-arm/cmse-implib-errors.out,
	* testsuite/ld-arm/cmse-new-earlier-later-implib.out,
	* testsuite/ld-arm/cmse-new-implib-not-sg-in-implib.out,
	* testsuite/ld-arm/cmse-new-wrong-implib.out,
	* testsuite/ld-arm/cmse-veneers-no-gnu_sgstubs.out,
	* testsuite/ld-arm/cmse-veneers-wrong-entryfct.out,
	* testsuite/ld-cris/badgotr1.d,
	* testsuite/ld-cris/tls-err-24.d,
	* testsuite/ld-cris/tls-err-25.d,
	* testsuite/ld-cris/tls-err-26.d,
	* testsuite/ld-cris/tls-err-27.d,
	* testsuite/ld-cris/tls-err-28.d,
	* testsuite/ld-cris/tls-err-40.d,
	* testsuite/ld-cris/tls-err-44.d,
	* testsuite/ld-cris/tls-err-48.d,
	* testsuite/ld-cris/tls-err-52.d,
	* testsuite/ld-cris/tls-err-53.d,
	* testsuite/ld-cris/tls-err-55.d,
	* testsuite/ld-cris/tls-err-56.d,
	* testsuite/ld-cris/tls-err-62.d,
	* testsuite/ld-cris/tls-err-65.d,
	* testsuite/ld-cris/tls-err-77.d,
	* testsuite/ld-elf/empty-implib.out,
	* testsuite/ld-elf/indirect.exp: Update.
2018-02-26 09:33:15 +10:30
Alan Modra
2c1c967956 MIPS messages
More standardization of messages.

bfd/
	* elfxx-mips.c: Standardize error/warning messages.
binutils/
	* testsuite/binutils-all/mips/mips-reginfo-n32.d,
	* testsuite/binutils-all/mips/mips-reginfo.d: Update.
gas/
	* testsuite/gas/mips/reginfo-2.l: Update.
ld/
	* testsuite/ld-mips-elf/attr-gnu-4-12.d,
	* testsuite/ld-mips-elf/attr-gnu-4-13.d,
	* testsuite/ld-mips-elf/attr-gnu-4-14.d,
	* testsuite/ld-mips-elf/attr-gnu-4-16.d,
	* testsuite/ld-mips-elf/attr-gnu-4-17.d,
	* testsuite/ld-mips-elf/attr-gnu-4-18.d,
	* testsuite/ld-mips-elf/attr-gnu-4-19.d,
	* testsuite/ld-mips-elf/attr-gnu-4-21.d,
	* testsuite/ld-mips-elf/attr-gnu-4-23.d,
	* testsuite/ld-mips-elf/attr-gnu-4-24.d,
	* testsuite/ld-mips-elf/attr-gnu-4-25.d,
	* testsuite/ld-mips-elf/attr-gnu-4-26.d,
	* testsuite/ld-mips-elf/attr-gnu-4-27.d,
	* testsuite/ld-mips-elf/attr-gnu-4-28.d,
	* testsuite/ld-mips-elf/attr-gnu-4-29.d,
	* testsuite/ld-mips-elf/attr-gnu-4-31.d,
	* testsuite/ld-mips-elf/attr-gnu-4-32.d,
	* testsuite/ld-mips-elf/attr-gnu-4-34.d,
	* testsuite/ld-mips-elf/attr-gnu-4-35.d,
	* testsuite/ld-mips-elf/attr-gnu-4-36.d,
	* testsuite/ld-mips-elf/attr-gnu-4-37.d,
	* testsuite/ld-mips-elf/attr-gnu-4-38.d,
	* testsuite/ld-mips-elf/attr-gnu-4-39.d,
	* testsuite/ld-mips-elf/attr-gnu-4-41.d,
	* testsuite/ld-mips-elf/attr-gnu-4-42.d,
	* testsuite/ld-mips-elf/attr-gnu-4-43.d,
	* testsuite/ld-mips-elf/attr-gnu-4-45.d,
	* testsuite/ld-mips-elf/attr-gnu-4-46.d,
	* testsuite/ld-mips-elf/attr-gnu-4-47.d,
	* testsuite/ld-mips-elf/attr-gnu-4-48.d,
	* testsuite/ld-mips-elf/attr-gnu-4-49.d,
	* testsuite/ld-mips-elf/attr-gnu-4-52.d,
	* testsuite/ld-mips-elf/attr-gnu-4-53.d,
	* testsuite/ld-mips-elf/attr-gnu-4-54.d,
	* testsuite/ld-mips-elf/attr-gnu-4-58.d,
	* testsuite/ld-mips-elf/attr-gnu-4-59.d,
	* testsuite/ld-mips-elf/attr-gnu-4-61.d,
	* testsuite/ld-mips-elf/attr-gnu-4-62.d,
	* testsuite/ld-mips-elf/attr-gnu-4-63.d,
	* testsuite/ld-mips-elf/attr-gnu-4-64.d,
	* testsuite/ld-mips-elf/attr-gnu-4-68.d,
	* testsuite/ld-mips-elf/attr-gnu-4-69.d,
	* testsuite/ld-mips-elf/attr-gnu-4-71.d,
	* testsuite/ld-mips-elf/attr-gnu-4-72.d,
	* testsuite/ld-mips-elf/attr-gnu-4-73.d,
	* testsuite/ld-mips-elf/attr-gnu-4-74.d,
	* testsuite/ld-mips-elf/attr-gnu-4-78.d,
	* testsuite/ld-mips-elf/attr-gnu-4-79.d,
	* testsuite/ld-mips-elf/attr-gnu-4-81.d,
	* testsuite/ld-mips-elf/attr-gnu-4-89.d,
	* testsuite/ld-mips-elf/attr-gnu-8-12.d,
	* testsuite/ld-mips-elf/attr-gnu-8-21.d,
	* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n32.d,
	* testsuite/ld-mips-elf/bal-jalx-pic-micromips-n64.d,
	* testsuite/ld-mips-elf/bal-jalx-pic-micromips.d,
	* testsuite/ld-mips-elf/bal-jalx-pic-n32.d,
	* testsuite/ld-mips-elf/bal-jalx-pic-n64.d,
	* testsuite/ld-mips-elf/bal-jalx-pic.d,
	* testsuite/ld-mips-elf/mode-change-error-1.d,
	* testsuite/ld-mips-elf/unaligned-branch-2.d,
	* testsuite/ld-mips-elf/unaligned-branch-ignore-2.d,
	* testsuite/ld-mips-elf/unaligned-branch-ignore-micromips.d,
	* testsuite/ld-mips-elf/unaligned-branch-ignore-mips16.d,
	* testsuite/ld-mips-elf/unaligned-branch-ignore-r6-1.d,
	* testsuite/ld-mips-elf/unaligned-branch-micromips.d,
	* testsuite/ld-mips-elf/unaligned-branch-mips16.d,
	* testsuite/ld-mips-elf/unaligned-branch-r6-1.d,
	* testsuite/ld-mips-elf/unaligned-branch-r6-2.d,
	* testsuite/ld-mips-elf/unaligned-branch.d,
	* testsuite/ld-mips-elf/unaligned-jalx-1.d,
	* testsuite/ld-mips-elf/unaligned-jalx-3.d,
	* testsuite/ld-mips-elf/unaligned-jalx-addend-1.d,
	* testsuite/ld-mips-elf/unaligned-jalx-addend-3.d,
	* testsuite/ld-mips-elf/unaligned-jalx-addend-micromips-1.d,
	* testsuite/ld-mips-elf/unaligned-jalx-addend-mips16-1.d,
	* testsuite/ld-mips-elf/unaligned-jalx-micromips-1.d,
	* testsuite/ld-mips-elf/unaligned-jalx-mips16-1.d,
	* testsuite/ld-mips-elf/unaligned-jump-micromips.d,
	* testsuite/ld-mips-elf/unaligned-jump-mips16.d,
	* testsuite/ld-mips-elf/unaligned-jump.d: Update.
2018-02-26 09:31:04 +10:30
Nick Clifton
340d33e565 Document the assembler's .dc, .dcb and .ds directives.
* doc/as.texinfo (Pseudo Ops): Add nodes for .dc, .dcb and .ds.
2018-02-23 10:43:53 +00:00
Kuan-Lin Chen
e859f6558c nds32: Support target directive .ict_model. 2018-02-23 14:27:13 +08:00
Andre Simoes Dias Vieira
7bdf778b10 Diagnose when trying to assemble conditional FP16 vmovx and vins
This patch makes GAS emit a warning when trying to assemble the Armv8.2
FP16 instructions VMOVX and VINS with condition codes. The Armv8-A
Reference Manual specifies these instructions without conditional codes
and says that if they are found in an IT block that they are CONSTRAINED
UNPREDICABLE.

gas/ChangeLog:
2018-02-22  Andre Vieira  <andre.simoesdiasvieira@arm.com>

	* config/tc-arm.c (do_neon_movhf): If conditional error out when in arm
	mode and emit warning in thumb mode.
	* testsuite/gas/arm/armv8-2-fp16-scalar-bad.s: Add new tests.
	* testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: Idem.
2018-02-22 16:34:36 +00:00