gas/
* config/tc-csky.c (get_operand_value): Add handler for
OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
* testsuite/gas/csky/csky_vdsp.d : Fix the disassembling
for vector register.
opcodes/
* csky-dis.c (csky_output_operand): Add handler for
OPRND_TYPE_IMM5b_VSH and OPRND_TYPE_VREG_WITH_INDEX.
* csky-opc.h (OPRND_TYPE_VREG_WITH_INDEX): New enum.
(OPRND_TYPE_IMM5b_VSH): New enum.
(csky_v2_opcodes): Fix and add some instructions for VDSPV1.
Change-Id: Ia5675d7b716fe5c331e6121ad8f83061ef6454bb
bfd * po/es.po: Fix printf format
binutils * windmc.c: Fix printf format
gas * config/tc-arc.c: Fix printf format
opcodes * po/es.po: Fix printf format
sim * arm/armos.c: Fix printf format
* ppc/emul_netbsd.c: Fix printf format
--
Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK
Always clear the slot 1 if it was assigned to the input file before the
first .file <NUMBER> directive has been seen. Always use as_where to
generate the correct debug infor for preprocessed assembly codes.
PR gas/25878
PR gas/26740
* dwarf2dbg.c (allocate_filename_to_slot): Don't reuse the slot 1
here.
(dwarf2_where): Restore as_where.
(dwarf2_directive_filename): Clear the slot 1 if it was assigned
to the input file.
* testsuite/gas/i386/dwarf5-line-2.d: New file.
* testsuite/gas/i386/dwarf5-line-2.s: Likewise.
* testsuite/gas/i386/dwarf5-line-3.d: Likewise.
* testsuite/gas/i386/dwarf5-line-3.s: Likewise.
* testsuite/gas/i386/i386.exp: Run dwarf5-line-2 and
dwarf5-line-3.
Some instructions can be emitted (dwarf2_emit_insn is called) before the
first .file <NUMBER> directive has been seen, which allocates the input
file as the first file entry. Reuse the input file entry in the file
table.
PR gas/25878
PR gas/26740
* dwarf2dbg.c (file_entry): Remove auto_assigned.
(assign_file_to_slot): Remove the auto_assign argument.
(allocate_filenum): Updated.
(allocate_filename_to_slot): Reuse the input file entry in the
file table.
(dwarf2_where): Replace as_where with as_where_physical.
* testsuite/gas/i386/dwarf5-line-1.d: New file.
* testsuite/gas/i386/dwarf5-line-1.s: Likewise.
* testsuite/gas/i386/i386.exp: Run dwarf5-line-1.
Rename VexOpcode to OpcodePrefix so that OpcodePrefix can be used for
regular encoding prefix.
gas/
* config/tc-i386.c (build_vex_prefix): Replace vexopcode with
opcodeprefix.
(build_evex_prefix): Likewise.
(is_any_vex_encoding): Don't check vexopcode.
(output_insn): Handle opcodeprefix.
opcodes/
* i386-gen.c (opcode_modifiers): Replace VexOpcode with
OpcodePrefix.
* i386-opc.h (VexOpcode): Renamed to ...
(OpcodePrefix): This.
(PREFIX_NONE): New.
(PREFIX_0X66): Likewise.
(PREFIX_0XF2): Likewise.
(PREFIX_0XF3): Likewise.
* i386-opc.tbl (Prefix_0X66): New.
(Prefix_0XF2): Likewise.
(Prefix_0XF3): Likewise.
Replace VexOpcode= with OpcodePrefix=. Use Prefix_0X66 on xorpd.
Use Prefix_0XF3 on cvtdq2pd. Use Prefix_0XF2 on cvtpd2dq.
* i386-tbl.h: Regenerated.
This patch fixes a bogus use of type punning in parse_barrier() which
was causing an assembly failure on big endian LP64 hosts when attempting
to assemble "isb sy" for AArch64.
The type of the entries in aarch64_barrier_opt_hsh is
aarch64_name_value_pair. We were incorrectly casting this to the
locally-defined asm_barrier_opt which has a wider type (on LP64) for the
second member. This happened to work on little-endian hosts but fails on
LP64 big endian.
The fix is to use the correct type in parse_barrier(). This makes the
locally-defined asm_barrier_opt redundant, so remove it.
gas/ChangeLog:
* config/tc-aarch64.c (asm_barrier_opt): Delete.
(parse_barrier): Fix bogus type punning.
* testsuite/gas/aarch64/system.d: Update disassembly.
* testsuite/gas/aarch64/system.s: Add isb sy test.
PR 26692
* config/tc-z80.c (md_begin): Ensure that xpressions are empty
before using them.
(unify_indexed): Likewise.
(z80_start_line_hook): Improve hash sign handling when SDCC
compatibility mode enabled.
(md_parse_exp_not_indexed): Improve indirect addressing
detection.
(md_pseudo_table): Accept hd64 as an alias of z810.
In 64bit, assembler generates a warning for "sysret":
$ echo sysret | as --64 -o x.o -
{standard input}: Assembler messages:
{standard input}:1: Warning: no instruction mnemonic suffix given and no register operands; using default for `sysret'
Always display suffix for %LQ in 64bit to display "sysretl".
gas/
PR binutils/26704
* testsuite/gas/i386/noreg64-data16.d: Expect sysretl instead of
sysret.
* testsuite/gas/i386/noreg64.d: Likewise.
* testsuite/gas/i386/x86-64-intel64.d: Likewise.
* testsuite/gas/i386/x86-64-opcode.d: Likewise.
opcodes/
PR binutils/26704
* i386-dis.c (putop): Always display suffix for %LQ in 64bit.
The MODRM byte can be checked to display the instruction name only if the
MODRM byte needed. Clear modrm if the MODRM byte isn't needed so that
modrm field checks in putop like, modrm.mod == N with N != 0, can be done
without checking need_modrm.
gas/
PR binutils/26705
* testsuite/gas/i386/x86-64-suffix.s: Add "mov %rsp,%rbp" before
sysretq.
* testsuite/gas/i386/x86-64-suffix-intel.d: Updated.
* testsuite/gas/i386/x86-64-suffix.d: Likewise.
opcodes/
PR binutils/26705
* i386-dis.c (print_insn): Clear modrm if not needed.
(putop): Check need_modrm for modrm.mod != 3. Don't check
need_modrm for modrm.mod == 3.
PR 26253
gas * config/obj-elf.c (obj_elf_section): Accept a numeric value for
the "o" section flag. Interpret it as a section index. Allow an
index of zero.
* doc/as.texi: Document the new behaviour.
* NEWS: Mention the new feature. Tidy entries.
* testsuite/gas/elf/sh-link-zero.s: New test.
* testsuite/gas/elf/sh-link-zero.d: New test driver.
* testsuite/gas/elf/elf.exp: Run the new test.
* testsuite/gas/elf/section21.l: Updated expected assembler
output.
bfd * elf.c (_bfd_elf_setup_sections): Do not complain about an
sh_link value of zero when the SLF_LINK_ORDER flag is set.
(assign_section_numbers): Likewise.
When the address size prefix applies to both the memory and the register
operand, we need to extract the address size prefix from the register
operand if the memory operand has no real registers, like symbol, DISP
or symbol(%rip).
NB: GCC always generates symbol(%rip) for RIP-relative addressing for
both x32 and x86-64.
Move the .code16 tests in movdir.s to movdir-16bit to show the correct
output from objdump.
PR gas/26685
* config/tc-i386.c (process_suffix): Also check the register
operand for the address size prefix if the memory operand has
no real registers.
* testsuite/gas/i386/enqcmd-16bit.d: New file.
* testsuite/gas/i386/enqcmd-16bit.s: Likewise.
* testsuite/gas/i386/movdir-16bit.d: Likewise.
* testsuite/gas/i386/movdir-16bit.s: Likewise.
* testsuite/gas/i386/enqcmd.s: Add tests with symbol and DISP.
* testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/movdir.s: Add tests with symbol and DISP.
Remove the .code16 test.
* testsuite/gas/i386/i386.exp: Run movdir-16bit and enqcmd-16bit.
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated.
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* testsuite/gas/i386/enqcmd-intel.d: Likewise.
* testsuite/gas/i386/enqcmd.d: Likewise.
* testsuite/gas/i386/movdir-intel.d: Likewise.
* testsuite/gas/i386/movdir.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
* config/obj-elf (elf_pseudo_table): Add attach_to_group.
(obj_elf_attach_to_group): New function.
* doc/as.texi: Document the new directive.
* NEWS: Mention the new feature.
* testsuite/gas/elf/attach-1.s: New test.
* testsuite/gas/elf/attach-1.d: New test driver.
* testsuite/gas/elf/attach-2.s: New test.
* testsuite/gas/elf/attach-2.d: New test driver.
* testsuite/gas/elf/attach-err.s: New test.
* testsuite/gas/elf/attach-err.d: New test driver.
* testsuite/gas/elf/attach-err.err: New test error output.
* testsuite/gas/elf/elf.exp: Run the new tests.
If the address prefix changes the register operand, we need to check the
register operand when the memory operand is RIP-relative.
PR gas/26685
* config/tc-i386.c (process_suffix): Check the register operand
for the address size prefix if the memory operand is symbol(%rip).
* testsuite/gas/i386/x86-64-enqcmd.s: Add tests with RIP-relative
addressing.
* testsuite/gas/i386/x86-64-movdir.s: Likewise.
* testsuite/gas/i386/x86-64-enqcmd-intel.d: Updated.
* testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
* testsuite/gas/i386/x86-64-movdir-intel.d: Likewise.
* testsuite/gas/i386/x86-64-movdir.d: Likewise.
This patch adds support for Arm's Neoverse N2 CPU to AArch64 binutils.
gas/ChangeLog:
* config/tc-aarch64.c (aarch64_cpus): Add neoverse-n2.
* doc/c-aarch64.texi: Document support for Neoverse N2.
gas * testsuite/gas/aarch64/ete.d: New test.
* testsuite/gas/aarch64/ete.s: New test.
opcodes * aarch64-opc.c: Add ETE system registers TRCEXTINSELR<0-3> and TRCRSR.
gas * testsuite/gas/aarch64/trbe-invalid.d: New test.
* testsuite/gas/aarch64/trbe-invalid.l: New test.
* testsuite/gas/aarch64/trbe-invalid.s: New test.
* testsuite/gas/aarch64/trbe.d: New test.
* testsuite/gas/aarch64/trbe.s: New test.
opcodes * aarch64-opc.c: Add TRBE system registers TRBIDR_EL1 , TRBBASER_EL1 ,
TRBLIMITR_EL1 , TRBMAR_EL1 , TRBPTR_EL1, TRBSR_EL1 and TRBTRG_EL1.
This simple follow-on patch adds a feature bit (FP16) that was missing
from the initial Neoverse V1 support.
gas/ChangeLog:
* config/tc-arm.c (arm_cpus): Add FP16 to Neoverse V1.
This simple follow-on patch groups the Neoverse cores together and adds
a missing feature bit (F16) to the entry for Neoverse V1.
gas/ChangeLog:
* config/tc-aarch64.c (aarch64_cpus): Group Neoverse cores
together, add missing F16 bit to Neoverse V1.
Emit an error instead of crashing in frag_new, handling this same as the
i386 port.
gas/
PR 26400
* config/tc-riscv.c (append_insn): If in absolute section, emit
error before add_relaxed_insn call.
* testsuite/gas/riscv/absolute-sec.d: New.
* testsuite/gas/riscv/absolute-sec.l: New.
* testsuite/gas/riscv/absolute-sec.s: New.
This patch adds support for Arm's Neoverse V1 CPU to AArch32 binutils.
gas/ChangeLog:
2020-09-24 Alex Coplan <alex.coplan@arm.com>
* config/tc-arm.c (arm_cpus): Add Neoverse V1.
* doc/c-arm.texi: Document Neoverse V1 support.
This adds support for Arm's Neoverse V1 CPU to AArch64 binutils.
gas/ChangeLog:
2020-09-24 Alex Coplan <alex.coplan@arm.com>
* config/tc-aarch64.c (aarch64_cpu_option_table): Add Neoverse V1.
* doc/c-aarch64.texi: Document Neoverse V1 support.
This adds support for Arm's Neoverse N2 CPU to AArch32 binutils. The
Neoverse N2 CPU builds AArch32 at EL0 and therefore needs support in the
AArch32 assembler.
gas/ChangeLog:
2020-09-24 Alex Coplan <alex.coplan@arm.com>
* config/tc-arm.c (arm_cpus): Add Neoverse N2.
* doc/c-arm.texi: Document -mcpu=neoverse-n2.
Add option parser for disassembler, and refine the codes of
parse register operand and disassemble register operand.
While strengthen the operands legality check of some instructions.
Co-Authored-By: Lifang Xia <lifang_xia@c-sky.com>
gas/
* config/tc-csky.c (parse_type_ctrlreg): Use function
csky_get_control_regno to operand.
(csky_get_reg_val): Likewise.
(is_reg_sp_with_bracket): Use function csky_get_reg_val
to parse operand.
(is_reg_sp): Refine.
(is_oimm_within_range): Fix, report error when operand
is not constant.
(parse_type_cpreg): Refine.
(parse_type_cpcreg): Refine.
(get_operand_value): Add handle of OPRND_TYPE_IMM5b_LS.
(md_assemble): Fix no error reporting somtimes when
operands number are not fit.
(csky_addc64): Refine.
(csky_subc64): Refine.
(csky_or64): Refine.
(v1_work_fpu_fo): Refine.
(v1_work_fpu_read): Refine.
(v1_work_fpu_writed): Refine.
(v1_work_fpu_readd): Refine.
(v2_work_addc): New function, strengthen the operands legality
check of addc.
* gas/testsuite/gas/csky/all.d : Use register number format when
disassemble register name by default.
* gas/testsuite/gas/csky/cskyv2_all.d : Likewise.
* gas/testsuite/gas/csky/trust.d: Likewise.
* gas/testsuite/gas/csky/cskyv2_ck860.d : Fix.
* gas/testsuite/gas/csky/trust.s : Fix.
opcodes/
* csky-dis.c (using_abi): New.
(parse_csky_dis_options): New function.
(get_gr_name): New function.
(get_cr_name): New function.
(csky_output_operand): Use get_gr_name and get_cr_name to
disassemble and add handle of OPRND_TYPE_IMM5b_LS.
(print_insn_csky): Parse disassembler options.
* opcodes/csky-opc.h (OPRND_TYPE_IMM5b_LS): New enum.
(GENARAL_REG_BANK): Define.
(REG_SUPPORT_ALL): Define.
(REG_SUPPORT_ALL): New.
(ASH): Define.
(REG_SUPPORT_A): Define.
(REG_SUPPORT_B): Define.
(REG_SUPPORT_C): Define.
(REG_SUPPORT_D): Define.
(REG_SUPPORT_E): Define.
(csky_abiv1_general_regs): New.
(csky_abiv1_control_regs): New.
(csky_abiv2_general_regs): New.
(csky_abiv2_control_regs): New.
(get_register_name): New function.
(get_register_number): New function.
(csky_get_general_reg_name): New function.
(csky_get_general_regno): New function.
(csky_get_control_reg_name): New function.
(csky_get_control_regno): New function.
(csky_v2_opcodes): Prefer two oprerans format for bclri and
bseti, strengthen the operands legality check of addc, zext
and sext.
