Christoph Müllner 5ec6edd0a2 RISC-V: Add support for the Zvksed ISA extension
Zvksed is part of the vector crypto extensions.

This extension adds the following instructions:
- vsm4k.vi
- vsm4r.[vv,vs]

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvksed.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvksed.d: New test.
	* testsuite/gas/riscv/zvksed.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VSM4K_VI): New.
	(MASK_VSM4K_VI): New.
	(MATCH_VSM4R_VS): New.
	(MASK_VSM4R_VS): New.
	(MATCH_VSM4R_VV): New.
	(MASK_VSM4R_VV): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction class
	support for Zvksed.

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvksed instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01 07:28:40 -06:00
..
2022-07-09 20:10:47 +09:30
2023-04-12 18:45:09 +03:00
2022-01-01 12:49:07 -05:00
2022-11-02 09:19:20 +08:00
2023-06-21 08:32:13 +02:00
2023-05-23 14:43:23 +08:00
2023-05-23 14:43:23 +08:00
2023-05-23 14:43:23 +08:00
2023-03-16 17:30:19 +10:30
2023-03-16 17:30:19 +10:30