Victor Do Nascimento a9e2cefdf0 aarch64: Implement TLBIP 128-bit instruction ...

The addition of 128-bit page table descriptors and, with it, the
addition of 128-bit system registers for these means that special
"invalidate translation table entry" instructions are needed to cope
with the new 128-bit model.  This is introduced with the `tlbpi'
instruction, implemented here.

2024-01-09 10:16:40 +00:00

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aout

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cgen

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coff

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elf

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gdb

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mach-o

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opcode

aarch64: Implement TLBIP 128-bit instruction

2024-01-09 10:16:40 +00:00

sim

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som

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vms

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alloca-conf.h

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ansidecl.h

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bfdlink.h

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binary-io.h

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bout.h

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ChangeLog

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ChangeLog-0415

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collectorAPI.h

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COPYING

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COPYING3

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ctf-api.h

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ctf.h

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demangle.h

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diagnostics.h

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dis-asm.h

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dwarf2.def

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dwarf2.h

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dyn-string.h

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environ.h

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fibheap.h

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filenames.h

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floatformat.h

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fnmatch.h

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fopen-bin.h

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fopen-same.h

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fopen-vms.h

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gcc-c-fe.def

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gcc-c-interface.h

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gcc-cp-fe.def

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gcc-cp-interface.h

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gcc-interface.h

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getopt.h

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hashtab.h

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hp-symtab.h

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leb128.h

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libcollector.h

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libfcollector.h

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libiberty.h

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longlong.h

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lto-symtab.h

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MAINTAINERS

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md5.h

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oasys.h

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objalloc.h

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obstack.h

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os9k.h

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partition.h

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plugin-api.h

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safe-ctype.h

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sframe-api.h

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sframe.h

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sha1.h

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simple-object.h

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sort.h

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splay-tree.h

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symcat.h

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timeval-utils.h

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vtv-change-permission.h

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xregex2.h

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xregex.h

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xtensa-config.h

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xtensa-dynconfig.h

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xtensa-isa-internal.h

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xtensa-isa.h

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