Jeff Law 37d6ee9350 Fix right shifts in mcore simulator on 64 bit hosts.
If the value to be shifted has the sign bit set, the sign
bit would get copied into bits 32..63 of the temporary.  Those
would then be right shifted into the final value giving an
incorrect final result.

This was observed with upcoming GCC improvements which eliminate
unnecessary extensions.
2023-12-01 07:19:50 -07:00
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