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Christoph Müllner fce8fef965 RISC-V: Add support for the Zvkned ISA extension 
Zvkned is part of the vector crypto extensions.

This extension adds the following instructions:
- vaesef.[vv,vs]
- vaesem.[vv,vs]
- vaesdf.[vv,vs]
- vaesdm.[vv,vs]
- vaeskf1.vi
- vaeskf2.vi
- vaesz.vs

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
	class support for Zvkned.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* testsuite/gas/riscv/zvkned.d: New test.
	* testsuite/gas/riscv/zvkned.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_VAESDF_VS): New.
	(MASK_VAESDF_VS): New.
	(MATCH_VAESDF_VV): New.
	(MASK_VAESDF_VV): New.
	(MATCH_VAESDM_VS): New.
	(MASK_VAESDM_VS): New.
	(MATCH_VAESDM_VV): New.
	(MASK_VAESDM_VV): New.
	(MATCH_VAESEF_VS): New.
	(MASK_VAESEF_VS): New.
	(MATCH_VAESEF_VV): New.
	(MASK_VAESEF_VV): New.
	(MATCH_VAESEM_VS): New.
	(MASK_VAESEM_VS): New.
	(MATCH_VAESEM_VV): New.
	(MASK_VAESEM_VV): New.
	(MATCH_VAESKF1_VI): New.
	(MASK_VAESKF1_VI): New.
	(MATCH_VAESKF2_VI): New.
	(MASK_VAESKF2_VI): New.
	(MATCH_VAESZ_VS): New.
	(MASK_VAESZ_VS): New.
	(DECLARE_INSN): New.
	* opcode/riscv.h (enum riscv_insn_class): Add instruction class
	support for Zvkned.

opcodes/ChangeLog:

	* riscv-opc.c: Add Zvkned instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-07-01 07:28:40 -06:00
..
aarch64.h
aarch64: Remove stray reglist variable
2023-03-30 17:01:30 +01:00
alpha.h
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2023-01-01 21:50:11 +10:30
arc-attrs.h
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arc-func.h
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arc.h
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arm.h
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avr.h
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bfin.h
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2023-01-01 21:50:11 +10:30
cgen.h
bpf: fix error conversion from long unsigned int to unsigned int [-Werror=overflow]
2023-02-03 11:18:50 -06:00
ChangeLog-0415
binutils ChangeLog rotation
2016-01-01 22:59:17 +10:30
ChangeLog-9103
Add copyright notices
2012-12-10 12:48:03 +00:00
convex.h
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2023-01-01 21:50:11 +10:30
cr16.h
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cris.h
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crx.h
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csky.h
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d10v.h
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d30v.h
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dlx.h
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ft32.h
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h8300.h
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hppa.h
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i386.h
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ia64.h
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loongarch.h
LoongArch: gas: Add LVZ and LBT instructions support
2023-06-30 17:32:28 +08:00
m68hc11.h
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m68k.h
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metag.h
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mips.h
Add MIPS Allegrex CPU as a MIPS2-based CPU
2023-06-15 04:45:03 +01:00
mmix.h
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mn10200.h
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mn10300.h
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moxie.h
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msp430-decode.h
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msp430.h
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nds32.h
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nfp.h
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nios2.h
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nios2r1.h
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nios2r2.h
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np1.h
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ns32k.h
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pdp11.h
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pj.h
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pn.h
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ppc.h
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pru.h
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pyr.h
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riscv-opc.h
RISC-V: Add support for the Zvkned ISA extension
2023-07-01 07:28:40 -06:00
riscv.h
RISC-V: Add support for the Zvkned ISA extension
2023-07-01 07:28:40 -06:00
rl78.h
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rx.h
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s12z.h
Enable building the s12z target on Solaris hosts where REG_Y is defined in system header files.
2020-01-02 12:04:40 +00:00
s390.h
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score-datadep.h
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score-inst.h
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sparc.h
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spu-insns.h
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spu.h
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tic4x.h
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tic6x-control-registers.h
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tic6x-insn-formats.h
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tic6x-opcode-table.h
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tic6x.h
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tic30.h
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tic54x.h
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tilegx.h
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tilepro.h
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v850.h
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vax.h
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visium.h
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wasm.h
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xgate.h
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