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Add UNSPEC_MASKOP to kupck<mode> instructions in sse.md on x86.

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This AVX512 specific patch to sse.md is split out from an earlier patch:
https://gcc.gnu.org/pipermail/gcc-patches/2022-June/596199.html

The new splitters proposed in that patch interfere with AVX512's
kunpckdq instruction which is defined as identical RTL,
DW:DI = (HI:SI<<32)|zero_extend(LO:SI).  To distinguish these,
and avoid AVX512 mask registers accidentally being (ab)used by reload
to perform SImode scalar shifts, this patch adds the explicit
(unspec UNSPEC_MASKOP) to the unpack mask operations, which matches
what sse.md does for the other mask specific (logic) operations.

2022-07-18  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
	* config/i386/sse.md (kunpckhi): Add UNSPEC_MASKOP unspec.
	(kunpcksi): Likewise, add UNSPEC_MASKOP unspec.
	(kunpckdi): Likewise, add UNSPEC_MASKOP unspec.
	(vec_pack_trunc_qi): Update to specify the now required
	UNSPEC_MASKOP unspec.
	(vec_pack_trunc_<mode>): Likewise.
This commit is contained in:
Roger Sayle
2022-07-18 07:36:13 +01:00
parent 6d7071776e
commit f9da2663f5
1 changed files with 22 additions and 14 deletions
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gcc/config/i386/sse.md
+22 -14
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@@ -2068,7 +2068,8 @@
(ashift:HI
(zero_extend:HI (match_operand:QI 1 "register_operand" "k"))
(const_int 8))
(zero_extend:HI (match_operand:QI 2 "register_operand" "k"))))]
(zero_extend:HI (match_operand:QI 2 "register_operand" "k"))))
(unspec [(const_int 0)] UNSPEC_MASKOP)]
"TARGET_AVX512F"
"kunpckbw\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "mode" "HI")
@@ -2081,7 +2082,8 @@
(ashift:SI
(zero_extend:SI (match_operand:HI 1 "register_operand" "k"))
(const_int 16))
(zero_extend:SI (match_operand:HI 2 "register_operand" "k"))))]
(zero_extend:SI (match_operand:HI 2 "register_operand" "k"))))
(unspec [(const_int 0)] UNSPEC_MASKOP)]
"TARGET_AVX512BW"
"kunpckwd\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "mode" "SI")])
@@ -2092,7 +2094,8 @@
(ashift:DI
(zero_extend:DI (match_operand:SI 1 "register_operand" "k"))
(const_int 32))
(zero_extend:DI (match_operand:SI 2 "register_operand" "k"))))]
(zero_extend:DI (match_operand:SI 2 "register_operand" "k"))))
(unspec [(const_int 0)] UNSPEC_MASKOP)]
"TARGET_AVX512BW"
"kunpckdq\t{%2, %1, %0|%0, %1, %2}"
[(set_attr "mode" "DI")])
@@ -17419,21 +17422,26 @@
})
(define_expand "vec_pack_trunc_qi"
[(set (match_operand:HI 0 "register_operand")
(ior:HI (ashift:HI (zero_extend:HI (match_operand:QI 2 "register_operand"))
(const_int 8))
(zero_extend:HI (match_operand:QI 1 "register_operand"))))]
[(parallel
[(set (match_operand:HI 0 "register_operand")
(ior:HI
(ashift:HI (zero_extend:HI (match_operand:QI 2 "register_operand"))
(const_int 8))
(zero_extend:HI (match_operand:QI 1 "register_operand"))))
(unspec [(const_int 0)] UNSPEC_MASKOP)])]
"TARGET_AVX512F")
(define_expand "vec_pack_trunc_<mode>"
[(set (match_operand:<DOUBLEMASKMODE> 0 "register_operand")
(ior:<DOUBLEMASKMODE>
(ashift:<DOUBLEMASKMODE>
[(parallel
[(set (match_operand:<DOUBLEMASKMODE> 0 "register_operand")
(ior:<DOUBLEMASKMODE>
(ashift:<DOUBLEMASKMODE>
(zero_extend:<DOUBLEMASKMODE>
(match_operand:SWI24 2 "register_operand"))
(match_dup 3))
(zero_extend:<DOUBLEMASKMODE>
(match_operand:SWI24 2 "register_operand"))
(match_dup 3))
(zero_extend:<DOUBLEMASKMODE>
(match_operand:SWI24 1 "register_operand"))))]
(match_operand:SWI24 1 "register_operand"))))
(unspec [(const_int 0)] UNSPEC_MASKOP)])]
"TARGET_AVX512BW"
{
operands[3] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode));