This probably has never actually affected anyone in practice. The normal
ABI implementation just uses malloc and only falls back to the pool on
malloc failure. But if that happens a bunch of times the freelist gets out
of order which violates some of the invariants of the freelist (as well as
the comments that follow the bug). The bug is just a comparison reversal
when traversing the freelist in the case where the pointer being returned
to the pool is after the existing freelist.
libstdc++-v3/
* libsupc++/eh_alloc.cc (pool::free): Inverse comparison.
We already had smin/smax RTL pattern using fmin/fmax instruction. But
for smin/smax, it's unspecified what will happen if either operand is
NaN. So we would generate calls to libc fmin/fmax functions with
-fno-finite-math-only (the default for all optimization levels expect
-Ofast).
But, LoongArch fmin/fmax instruction is IEEE-754-2008 conformant so we
can also use the instruction for fmin/fmax pattern and avoid the library
function call.
gcc/ChangeLog:
* config/loongarch/loongarch.md (fmax<mode>3): New RTL pattern.
(fmin<mode>3): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/fmax-fmin.c: New test.
Provide a routine to pick out the ssa-names from interesting statements.
* gimple-range-fold.cc (gimple_range_ssa_names): New.
* gimple-range-fold.h (gimple_range_ssa_names): New prototype.
* gimple-range-gori.cc (range_def_chain::get_def_chain): Move
code to new routine.
These tests are now passing.
gcc/testsuite/ChangeLog:
* g++.dg/warn/Wstringop-overflow-4.C: Only xfail for C++98.
* g++.target/i386/bfloat_cpp_typecheck.C: Remove xfail.
Gcc's '#pragma GCC diagnostic' directives are processed in "early mode"
(see handle_pragma_diagnostic_early) for the C++ frontend and, as such,
require that the target diagnostic option be enabled for the preprocessor
(see c_option_is_from_cpp_diagnostics). This change modifies the
-Wc++20-compat option definition to register it as a preprocessor option
so that its associated diagnostics can be suppressed. The changes also
implicitly disable the option in C++20 and later modes. These changes
are consistent with the definition of the -Wc++11-compat option.
This support is motivated by the need to suppress the following diagnostic
otherwise issued in C++17 and earlier modes due to the char8_t typedef
present in the uchar.h header file in glibc 2.36.
warning: identifier ‘char8_t’ is a keyword in C++20 [-Wc++20-compat]
Tests are added to validate suppression of both -Wc++11-compat and
-Wc++20-compat related diagnostics (fixes were only needed for the C++20
case).
PR c++/106423
gcc/c-family/ChangeLog:
* c-opts.cc (c_common_post_options): Disable -Wc++20-compat
diagnostics in C++20 and later.
* c.opt (Wc++20-compat): Enable hooks for the preprocessor.
gcc/cp/ChangeLog:
* parser.cc (cp_lexer_saving_tokens): Add comment regarding
diagnostic requirements.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/keywords2.C: New test.
* g++.dg/cpp2a/keywords2.C: New test.
libcpp/ChangeLog:
* include/cpplib.h (cpp_warning_reason): Add CPP_W_CXX20_COMPAT.
* init.cc (cpp_create_reader): Add cpp_warn_cxx20_compat.
As mentioned at https://gcc.gnu.org/PR106637#c2, the discontinued
providing binaries.
PR target/106637
gcc/ChangeLog:
* doc/install.texi: Remove link to www.bullfreeware.com
Zfh and Zfhmin are extensions for IEEE half precision, both are ratified
in Jan. 2022[1]:
- Zfh has full set of operation like F or D for single or double precision.
- Zfhmin has only provide minimal support for half precision operation,
like conversion, load, store and move instructions.
[1] https://github.com/riscv/riscv-isa-manual/commit/b35a54079e0da11740ce5b1e6db999d1d5172768
gcc/ChangeLog:
* common/config/riscv/riscv-common.cc (riscv_implied_info): Add
zfh and zfhmin.
(riscv_ext_version_table): Ditto.
(riscv_ext_flag_table): Ditto.
* config/riscv/riscv-opts.h (MASK_ZFHMIN): New.
(MASK_ZFH): Ditto.
(TARGET_ZFHMIN): Ditto.
(TARGET_ZFH): Ditto.
* config/riscv/riscv.cc (riscv_output_move): Handle HFmode move
for zfh and zfhmin.
(riscv_emit_float_compare): Handle HFmode.
* config/riscv/riscv.md (ANYF): Add HF.
(SOFTF): Add HF.
(load): Ditto.
(store): Ditto.
(truncsfhf2): New.
(truncdfhf2): Ditto.
(extendhfsf2): Ditto.
(extendhfdf2): Ditto.
(*movhf_hardfloat): Ditto.
(*movhf_softfloat): Make sure not ZFHMIN.
* config/riscv/riscv.opt (riscv_zf_subext): New.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/_Float16-zfh-1.c: New.
* gcc.target/riscv/_Float16-zfh-2.c: Ditto.
* gcc.target/riscv/_Float16-zfh-3.c: Ditto.
* gcc.target/riscv/_Float16-zfhmin-1.c: Ditto.
* gcc.target/riscv/_Float16-zfhmin-2.c: Ditto.
* gcc.target/riscv/_Float16-zfhmin-3.c: Ditto.
* gcc.target/riscv/arch-16.c: Ditto.
* gcc.target/riscv/arch-17.c: Ditto.
* gcc.target/riscv/predef-21.c: Ditto.
* gcc.target/riscv/predef-22.c: Ditto.
The backward threader copier cannot deal with the situation of
copying blocks belonging to different loops and will reject those
paths late. The following uses this to prune path discovery,
saving on compile-time. Note the off-loop block is still considered
as entry edge origin.
* tree-ssa-threadbackward.cc (back_threader::find_paths_to_names):
Do not walk further if we are leaving the current loop.
The bug appeared afte r13-2010-g1270ccda70ca09 "Factor out
jobserver_active_p" slightly changed `putenv()` use from allocating
to non-allocating:
-xputenv (concat ("MAKEFLAGS=", dup, NULL));
+xputenv (jinfo.skipped_makeflags.c_str ());
`xputenv()` (and `putenv()`) don't copy strings and only store the
pointer in the `environ` global table. As a result `environ` got
corrupted as soon as `jinfo.skipped_makeflags` store got deallocated.
This started causing bootstrap crashes in `execv()` calls:
xgcc: fatal error: cannot execute '/build/build/./prev-gcc/collect2': execv: Bad address
The change restores memory allocation for `xputenv()` argument.
gcc/
PR driver/106624
* gcc.cc (driver::detect_jobserver): Allocate storage xputenv()
argument using xstrdup().
From what I can see, this has been voted in as a DR and as it means
we warn less often than before in -std={gnu,c}++2{0,3} modes or with
-Wvolatile, I wonder if it shouldn't be backported to affected release
branches as well.
2022-08-16 Jakub Jelinek <jakub@redhat.com>
* typeck.cc (cp_build_modify_expr): Implement
P2327R1 - De-deprecating volatile compound operations. Don't warn
for |=, &= or ^= with volatile lhs.
* expr.cc (mark_use) <case MODIFY_EXPR>: Adjust warning wording,
leave out simple.
* g++.dg/cpp2a/volatile1.C: Adjust for de-deprecation of volatile
compound |=, &= and ^= operations.
* g++.dg/cpp2a/volatile3.C: Likewise.
* g++.dg/cpp2a/volatile5.C: Likewise.
The wiki links probably worked at some point in the distant past, but
now the official location of tracking all D Improvement Proposals is on
the upstream dlang/DIPs GitHub repository.
PR d/106638
gcc/d/ChangeLog:
* gdc.texi: Update DIP links to point at upstream dlang/DIPs
repository.
The purpose of this change is to disambiguate the imports name with
its use in GORI.
gcc/ChangeLog:
* gimple-range-path.cc (path_range_query::import_p): Rename to...
(path_range_query::exit_dependency_p): ...this.
(path_range_query::dump): Rename imports to exit dependencies.
(path_range_query::compute_ranges_in_phis): Same.
(path_range_query::compute_ranges_in_block): Same.
(path_range_query::adjust_for_non_null_uses): Same.
(path_range_query::compute_ranges): Same.
(path_range_query::compute_phi_relations): Same.
(path_range_query::add_to_imports): Rename to...
(path_range_query::add_to_exit_dependencies): ...this.
(path_range_query::compute_imports): Rename to...
(path_range_query::compute_exit_dependencies): ...this.
* gimple-range-path.h (class path_range_query): Rename imports to
exit dependencies.
Fixes:
gcc/value-range-storage.h:129:40: warning: class with destructor marked 'final' cannot be inherited from [-Wfinal-dtor-non-final-class]
gcc/value-range-storage.h:146:36: warning: class with destructor marked 'final' cannot be inherited from [-Wfinal-dtor-non-final-class]
gcc/ChangeLog:
* value-range-storage.h (class obstack_vrange_allocator): Mark
the class as final.
(class ggc_vrange_allocator): Likewise.
Add 2 virtual destructors in order to address:
gcc/alloc-pool.h:522:5: warning: destructor called on non-final 'value_range_equiv' that has virtual functions but non-virtual destructor [-Wdelete-non-abstract-non-virtual-dtor]
gcc/ggc.h:166:3: warning: destructor called on non-final 'int_range<1>' that has virtual functions but non-virtual destructor [-Wdelete-non-abstract-non-virtual-dtor]
gcc/ChangeLog:
* value-range-equiv.h (class value_range_equiv): Add virtual
destructor.
* value-range.h: Likewise.
The following avoids ping-pong between the match.pd pattern changing
(sizetype) ((a_9 + 1) * 48) to (sizetype)(a_9 + 1) * 48 and
extract_muldiv performing the reverse transform by restricting the
match.pd pattern to narrowing conversions as the comment indicates.
PR middle-end/106630
* match.pd ((T)(x * CST) -> (T)x * CST): Restrict to
narrowing conversions.
* gcc.dg/torture/pr106630.c: New testcase.
Address:
gcc/value-range-equiv.h:57:8: warning: 'set_undefined' overrides a member function but is not marked 'override' [-Winconsistent-missing-override]
gcc/value-range-equiv.h:58:8: warning: 'set_varying' overrides a member function but is not marked 'override' [-Winconsistent-missing-override]
gcc/ChangeLog:
* value-range-equiv.h (class value_range_equiv):
In c3ed9e0d6e, David added some
"final override" and since that there are 2 new warnings that
need the same treatment:
gcc/config/i386/i386-features.h:186:8: warning: 'convert_op' overrides a member function but is not marked 'override' [-Winconsistent-missing-override]
gcc/config/i386/i386-features.h:186:8: warning: 'convert_op' overrides a member function but is not marked 'override' [-Winconsistent-missing-override]
gcc/config/i386/i386-features.h:199:8: warning: 'convert_op' overrides a member function but is not marked 'override' [-Winconsistent-missing-override]
gcc/config/i386/i386-features.h:199:8: warning: 'convert_op' overrides a member function but is not marked 'override' [-Winconsistent-missing-override]
gcc/ChangeLog:
* config/i386/i386-features.h (class general_scalar_chain): Add
final override for a method.
(class timode_scalar_chain): Likewise.
The current jobserver_info relies on non-blocking FDs,
thus one the pipe in such mode.
gcc/ChangeLog:
* opts-common.cc (jobserver_info::connect): Open fifo
in non-blocking mode.
As PR103353 shows, we may want to continue to expand built-in
function __builtin_vsx_lxvp, even if we have already emitted
error messages about some missing required conditions. As
shown in that PR, without one explicit mov optab on OOmode
provided, it would call emit_move_insn recursively.
So this patch is to allow the mov pattern to be generated during
expanding phase if compiler has already seen errors.
PR target/103353
gcc/ChangeLog:
* config/rs6000/mma.md (define_expand movoo): Move TARGET_MMA condition
check to preparation statements and add handlings for !TARGET_MMA.
(define_expand movxo): Likewise.
gcc/testsuite/ChangeLog:
* gcc.target/powerpc/pr103353.c: New test.
As PR106322 shows, in some cases for some vector type whose
TYPE_MODE is a scalar integral mode instead of a vector mode,
it's possible to obtain wrong target support information when
querying with the scalar integral mode. For example, for the
test case in PR106322, on ppc64 32bit vectorizer gets vector
type "vector(2) short unsigned int" for scalar type "short
unsigned int", its mode is SImode instead of V2HImode. The
target support querying checks umul_highpart optab with SImode
and considers it's supported, then vectorizer further generates
.MULH IFN call for that vector type. Unfortunately it's wrong
to use SImode support for that vector type multiply highpart
here.
This patch is to teach vectorizable_call analysis not to allow
vect_emulated_vector_p type for both vectype_in and vectype_out
as Richi suggested.
PR tree-optimization/106322
gcc/ChangeLog:
* tree-vect-stmts.cc (vectorizable_call): Don't allow
vect_emulated_vector_p type for both vectype_in and vectype_out.
gcc/testsuite/ChangeLog:
* gcc.target/i386/pr106322.c: New test.
* gcc.target/powerpc/pr106322.c: New test.
Since GCC10, the "subreg2" optimization pass was no longer tied to enabling
"subreg1" unless -fsplit-wide-types-early was turned on (PR88233). However
on the Xtensa port, the lack of "subreg2" can degrade the quality of the
output code, especially for those that produce many D[FC]mode pseudos.
This patch turns on -fsplit-wide-types-early by default in order to restore
the previous behavior.
gcc/ChangeLog:
* common/config/xtensa/xtensa-common.cc
(xtensa_option_optimization_table): Add OPT_fsplit_wide_types_early
for OPT_LEVELS_ALL in order to restore pre-GCC10 behavior.
This is to prevent the case of when generating the methods of a struct
type, we don't accidentally emit an inline function that references it,
as the outer struct itself would still be incomplete.
gcc/d/ChangeLog:
* d-tree.h (d_defer_declaration): Declare.
* decl.cc (function_needs_inline_definition_p): Defer checking
DECL_UNINLINABLE and DECL_DECLARED_INLINE_P.
(maybe_build_decl_tree): Call d_defer_declaration instead of
build_decl_tree.
* modules.cc (deferred_inline_declarations): New variable.
(build_module_tree): Set deferred_inline_declarations and a handle
declarations pushed to it.
(d_defer_declaration): New function.
Because complex types are deprecated in the language, the new way to
expose native complex types is by defining an enum with a basetype of a
library-defined struct that is implicitly treated as-if it is native.
As casts are not implicitly added by the front-end when downcasting from
enum to its underlying type, we must insert an explicit cast during the
code generation pass.
PR d/106623
gcc/d/ChangeLog:
* d-codegen.cc (underlying_complex_expr): New function.
(d_build_call): Handle passing native complex objects as the
library-defined equivalent.
* d-tree.h (underlying_complex_expr): Declare.
* expr.cc (ExprVisitor::visit (DotVarExp *)): Call
underlying_complex_expr instead of build_vconvert.
gcc/testsuite/ChangeLog:
* gdc.dg/torture/pr106623.d: New test.
If for whatever reason the module declaration doesn't exist in the
object file, ensure that the internal definitions for TypeInfo and
TypeInfo_Class are still created, otherwise an ICE could occur later if
they are required for a run-time helper call.
gcc/d/ChangeLog:
* d-compiler.cc (Compiler::onParseModule): Call create_tinfo_types
when module name is object.
* typeinfo.cc (create_tinfo_types): Add guard for multiple
invocations.
Doesn't change anything in the code generation or ABI, but makes it
consistent with regular delegates as names would match up when
inspecting tree dumps.
gcc/d/ChangeLog:
* d-codegen.cc (build_delegate_cst): Give anonymous delegate field
names same as per ABI spec.
Fix a read/write typo.
Also, add more test coverage of -Wanalyzer-out-of-bounds to help
establish a baseline for experiments on tweaking the wording of
the warning (PR analyzer/106626).
gcc/analyzer/ChangeLog:
PR analyzer/106626
* region-model.cc (buffer_overread::emit): Fix copy&paste error in
direction of the access in the note.
gcc/testsuite/ChangeLog:
PR analyzer/106626
* gcc.dg/analyzer/out-of-bounds-read-char-arr.c: New test.
* gcc.dg/analyzer/out-of-bounds-read-int-arr.c: New test.
* gcc.dg/analyzer/out-of-bounds-write-char-arr.c: New test.
* gcc.dg/analyzer/out-of-bounds-write-int-arr.c: New test.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
gcc/analyzer/ChangeLog:
PR analyzer/106573
* region-model.cc (region_model::on_call_pre): Use check_call_args
when ensuring that we call get_arg_svalue on all args. Remove
redundant call from handling for stdio builtins.
Signed-off-by: David Malcolm <dmalcolm@redhat.com>
Rearrange order in irange:set to ensure all POLY_INTs map to varying.
PR tree-optimization/106621
gcc/
* value-range.cc (irange::set): Check for POLY_INT_CST early.
gcc/testsuite/
* gcc.dg/pr106621.c
This patch fixes the ICE caused by valid_to_unchecked_state
in sm-fd.cc by exiting early if first argument of any "dup"
functions is invalid.
gcc/analyzer/ChangeLog:
PR analyzer/106551
* sm-fd.cc (check_for_dup): exit early if first
argument is invalid for all dup functions.
gcc/testsuite/ChangeLog:
PR analyzer/106551
* gcc.dg/analyzer/fd-dup-1.c: New testcase.
Signed-off-by: Immad Mir <mirimmad@outlook.com>
This patch adds support for converting 128-bit TImode shifts and rotates
to SSE equivalents using V1TImode during the TImode STV pass.
Previously, only logical shifts by multiples of 8 were handled
(from my patch earlier this month).
As an example of the benefits, the following rotate by 32-bits:
unsigned __int128 a, b;
void rot32() { a = (b >> 32) | (b << 96); }
when compiled on x86_64 with -O2 previously generated:
movq b(%rip), %rax
movq b+8(%rip), %rdx
movq %rax, %rcx
shrdq $32, %rdx, %rax
shrdq $32, %rcx, %rdx
movq %rax, a(%rip)
movq %rdx, a+8(%rip)
ret
with this patch, now generates:
movdqa b(%rip), %xmm0
pshufd $57, %xmm0, %xmm0
movaps %xmm0, a(%rip)
ret
[which uses a V4SI permutation for those that don't read SSE].
This should help 128-bit cryptography codes, that interleave XORs
with rotations (but that don't use additions or subtractions).
2022-08-15 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/i386/i386-features.cc
(timode_scalar_chain::compute_convert_gain): Provide costs for
shifts and rotates.
(timode_scalar_chain::convert_insn): Handle ASHIFTRT, ROTATERT
and ROTATE just like existing ASHIFT and LSHIFTRT cases.
(timode_scalar_to_vector_candidate_p): Handle all shifts and
rotates by integer constants between 0 and 127.
gcc/testsuite/ChangeLog
* gcc.target/i386/sse4_1-stv-9.c: New test case.
This patch tweaks timode_scalar_chain::compute_convert_gain to provide
more accurate costs for converting TImode comparisons against zero or
minus 1 to V1TImode equivalents.
2022-08-15 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
* config/i386/i386-features.cc
(timode_scalar_chain::compute_convert_gain): Provide gains for
comparisons against 0/-1, including "*testti" patterns.
This patch resolves both PR tree-optimization/64992 and PR
tree-optimization/98956 which are missed optimization enhancement
request, for which Andrew Pinski already has a proposed solution
(related to a fix for PR tree-optimization/98954). Yesterday,
I proposed an alternate improved patch for PR98954, which although
superior in most respects, alas didn't address this case [which
doesn't include a BIT_AND_EXPR], hence this follow-up fix.
For many functions, F(B), of a (zero-one) Boolean value B, the
expression F(B) != 0 can often be simplified to just B. Hence
"(B * 5) != 0" is B, "-B != 0" is B, "bswap(B) != 0" is B,
"(B >>r 3) != 0" is B. These are all currently optimized by GCC,
with the strange exception of left shifts by a constant (possibly
due to the undefined/implementation defined behaviour when the
shift constant is larger than the first operand's precision).
This patch adds support for this particular case, when the shift
constant is valid.
2022-08-15 Roger Sayle <roger@nextmovesoftware.com>
gcc/ChangeLog
PR tree-optimization/64992
PR tree-optimization/98956
* match.pd (ne (lshift @0 @1) 0): Simplify (X << C) != 0 to X
when X is zero_one_valued_p and the shift constant C is valid.
(eq (lshift @0 @1) 0): Likewise, simplify (X << C) == 0 to !X
when X is zero_one_valued_p and the shift constant C is valid.
gcc/testsuite/ChangeLog
PR tree-optimization/64992
* gcc.dg/pr64992.c: New test case.
This patch is the first part of a solution to PR tree-optimization/71343,
a missed-optimization enhancement request where GCC fails to see that
(a<<2)+(b<<2) == a*4+b*4.
This piece is that (X<<C) op (Y<<C) can be simplified to (X op Y) << C,
for many binary operators, including AND, IOR, XOR, and (if overflow
isn't an issue) PLUS and MINUS. Likewise, the right shifts (both logical
and arithmetic) and bit-wise logical operators can be simplified in a
similar fashion. These all reduce the number of GIMPLE binary operations
from 3 to 2, by combining/eliminating a shift operation.
2022-08-15 Roger Sayle <roger@nextmovesoftware.com>
Richard Biener <rguenther@suse.de>
gcc/ChangeLog
PR tree-optimization/71343
* match.pd (op (lshift @0 @1) (lshift @2 @1)): Optimize the
expression (X<<C) + (Y<<C) to (X+Y)<<C for multiple operators.
(op (rshift @0 @1) (rshift @2 @1)): Likewise, simplify (X>>C)^(Y>>C)
to (X^Y)>>C for binary logical operators, AND, IOR and XOR.
gcc/testsuite/ChangeLog
PR tree-optimization/71343
* gcc.dg/pr71343-1.c: New test case.
Not all systems have the same injected headers, leading to line
location table differences that are immaterial to the test. Fix the
regexp more robustly.
gcc/testsuite/
* g++.dg/modules/loc-prune-4.C: Adjust regexp
We already have a warning that warns about pessimizing std::move
in a return statement, when it prevents the NRVO:
T fn()
{
T t;
return std::move (t); // warning \o/
}
However, the warning doesn't warn when what we are returning is a class
prvalue, that is, when std::move prevents the RVO:
T fn()
{
T t;
return std::move (T{}); // no warning :-(
}
This came up recently in GCC:
<https://gcc.gnu.org/pipermail/gcc-patches/2022-July/598177.html>.
This patch fixes that. I would like to extend the warning further, so
that it warns in more contexts, e.g.:
T t = std::move(T());
or
void foo (T);
foo (std::move(T()));
PR c++/106276
gcc/cp/ChangeLog:
* typeck.cc (can_do_rvo_p): New.
(maybe_warn_pessimizing_move): Warn when moving a temporary object
in a return statement prevents copy elision.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/Wpessimizing-move7.C: New test.
I've noticed that range_on_path_entry does mightly complicated things
that don't make sense to me and the commentary might just be
out of date. For the sake of it I replaced it with range_on_entry
and statistics show we thread _more_ jumps with that, so better
not do magic there.
* gimple-range-path.cc (range_on_path_entry): Just
call range_on_entry.
This patch continues the effort of cleaning up the testsuite for
--enable-default-pie; the focus herein is mostly 32-bit x86.
As much as I tried to avoid it, most of the changes to the testsuite
simply disable PIC/PIE, for reasons I'm going to detail below.
static-cdtor1.C gets new patterns to match PIE output. Some
avx512fp16 tests change only in register allocation, because of the
register used to hold the GOT base address. Interrupt tests changed
in this regard as well, but here it also affected register saving and
restoring.
The previous patch modified cet-sjlj tests, mentioning a single regexp
covering PIC and nonPIC got incorrect match counts. I found out that
adding ?: to parenthesized subpatterns avoids miscounting matches.
Other tests that count certain kinds of insns needed adjustment over
insns in get_pc_thunk, extra loads from the GOT, or extra adds to
compute addresses. In one case, namely stack-check-12, it is nonPIC
that had extra insns, that PIC gets rid of, or rather, pushing and
popping the PIC register obviates the dummy push and matching pop used
for stack probing in nonpic.
pr95126 tests were supposed to optimize loads into known constants,
but the @GOTOFF addresses prevent that for reasons I have not
investigated, but that would be clearly desirable, so I've XFAILed
these. pr95852 is another case of missed optimization: sibcalls are
not possible when the PIC register needs to be set up for the call,
which prevents the expected constant propagation to the return block;
I have adjusted the codegen expectations of these tests.
As for tests that disable PIE... Some are judgment calls, that fail
for similar reasons as tests described above, but I chose not to
adjust their expectations; others are just not possible with PIC, or
not worth the effort of adjusting.
anon[14].C check for no global or comdat symbols, respectively, but
-fPIE outputs get_pc_thunk, as global hidden comdat.
initlist-const1.C wants .rodata and checks for no .data, but PIC
outputs constant data that needs relocations in .data.rel.ro.local.
no-stack-protector-attr-3.C and stackprotectexplicit2.C count
stack_check_fail matches; -fPIE calls stack_check_fail_local instead,
which matches the pattern, but this symbol is also marked as .hidden,
so the match count needs to be adjusted.
pr71694.C checks for no movl, but get_pc_thunk contains one.
pr102892-1.c is a missed optimization, ivopts creates an induction
variable because the array address can't be part of an indexing base
address with PIE, and that ends up stopping a load from being resolved
to a constant as expected. sibcall-11.c needs @PLT for the call,
which requires the PIC register, which makes sibcalling impossible.
builtin-self.c, in turn, expects no calls, but PIC calls get_pc_thunk.
avx* vector tests that had PIE disabled were affected in that the need
for GOT-based addressing modes changed instruction selection in ways
that deviated from the expectations of the tests. Ditto other vector
tests: pr100865*, pr101796-1, pr101846, pr101989-broadcast-1, and
pr102021, pr54855-[37], and pr90773-17.
pr15184* tests need a PIC register to access global variables, which
affects register allocation, so the patterns would have to be
adjusted. pr27971 can't use the expected addressing mode to
dereference the array with PIC, so it ends up selecting an indexed
addressing mode, obviating the expected separate shift insn.
pr70263-2 is another case that implicitly expects a sibcall,
impossible because of the need for the PIC register; without a
sibcall, the expected REG_EQUIV for the reuse of the stack slot of an
incoming argument does not occur. pr78035 duplicates the final
compare in both then and else blocks with PIE, which deviates from the
expected cmp count. pr81736-[57] test for no frame pointer, but the
PIC register assignment to a call-saved register forces a frame; the
former ends up not using the PIC register, but it's only optimized out
after committing to a stack frame to preserve it. pr85620-6 also
expects a tail call in a situation that is impossible on ia32 PIC.
pr85667-6 doesn't expect the movl in get_pc_thunk. pr93492-5 tests
-mfentry, not available with PIC on ia32. pr96539 expects a
tail-call, to avoid copying a large-ish struct argument, but the call
requires the PIC register, so no tail-call. stack-prot-sym.c expects
a nonpic addressing mode.
for gcc/testsuite/ChangeLog
* g++.dg/abi/anon1.C: Disable pie on ia32.
* g++.dg/abi/anon4.C: Likewise.
* g++.dg/cpp0x/initlist-const1.C: Likewise.
* g++.dg/no-stack-protector-attr-3.C: Likewise.
* g++.dg/stackprotectexplicit2.C: Likewise.
* g++.dg/pr71694.C: Likewise.
* gcc.dg/pr102892-1.c: Likewise.
* gcc.dg/sibcall-11.c: Likewise.
* gcc.dg/torture/builtin-self.c: Likewise.
* gcc.target/i386/avx2-dest-false-dep-for-glc.c: Likewise.
* gcc.target/i386/avx512bf16-cvtsbh2ss-1.c: Likewise.
* gcc.target/i386/avx512f-broadcast-pr87767-1.c: Likewise.
* gcc.target/i386/avx512f-broadcast-pr87767-3.c: Likewise.
* gcc.target/i386/avx512f-broadcast-pr87767-5.c: Likewise.
* gcc.target/i386/avx512f-broadcast-pr87767-7.c: Likewise.
* gcc.target/i386/avx512fp16-broadcast-1.c: Likewise.
* gcc.target/i386/avx512fp16-pr101846.c: Likewise.
* gcc.target/i386/avx512vl-broadcast-pr87767-1.c: Likewise.
* gcc.target/i386/avx512vl-broadcast-pr87767-3.c: Likewise.
* gcc.target/i386/avx512vl-broadcast-pr87767-5.c: Likewise.
* gcc.target/i386/pr100865-2.c: Likewise.
* gcc.target/i386/pr100865-3.c: Likewise.
* gcc.target/i386/pr100865-4a.c: Likewise.
* gcc.target/i386/pr100865-4b.c: Likewise.
* gcc.target/i386/pr100865-5a.c: Likewise.
* gcc.target/i386/pr100865-5b.c: Likewise.
* gcc.target/i386/pr100865-6a.c: Likewise.
* gcc.target/i386/pr100865-6b.c: Likewise.
* gcc.target/i386/pr100865-6c.c: Likewise.
* gcc.target/i386/pr100865-7b.c: Likewise.
* gcc.target/i386/pr101796-1.c: Likewise.
* gcc.target/i386/pr101846-2.c: Likewise.
* gcc.target/i386/pr101989-broadcast-1.c: Likewise.
* gcc.target/i386/pr102021.c: Likewise.
* gcc.target/i386/pr90773-17.c: Likewise.
* gcc.target/i386/pr54855-3.c: Likewise.
* gcc.target/i386/pr54855-7.c: Likewise.
* gcc.target/i386/pr15184-1.c: Likewise.
* gcc.target/i386/pr15184-2.c: Likewise.
* gcc.target/i386/pr27971.c: Likewise.
* gcc.target/i386/pr70263-2.c: Likewise.
* gcc.target/i386/pr78035.c: Likewise.
* gcc.target/i386/pr81736-5.c: Likewise.
* gcc.target/i386/pr81736-7.c: Likewise.
* gcc.target/i386/pr85620-6.c: Likewise.
* gcc.target/i386/pr85667-6.c: Likewise.
* gcc.target/i386/pr93492-5.c: Likewise.
* gcc.target/i386/pr96539.c: Likewise.
PR target/81708 (%gs:my_guard)
* gcc.target/i386/stack-prot-sym.c: Likewise.
* g++.dg/init/static-cdtor1.C: Add alternate patterns for PIC.
* gcc.target/i386/avx512fp16-vcvtsh2si-1a.c: Extend patterns
for PIC/PIE register allocation.
* gcc.target/i386/pr100704-3.c: Likewise.
* gcc.target/i386/avx512fp16-vcvtsh2usi-1a.c: Likewise.
* gcc.target/i386/avx512fp16-vcvttsh2si-1a.c: Likewise.
* gcc.target/i386/avx512fp16-vcvttsh2usi-1a.c: Likewise.
* gcc.target/i386/avx512fp16-vmovsh-1a.c: Likewise.
* gcc.target/i386/interrupt-11.c: Likewise, allowing for
preservation of the PIC register.
* gcc.target/i386/interrupt-12.c: Likewise.
* gcc.target/i386/interrupt-13.c: Likewise.
* gcc.target/i386/interrupt-15.c: Likewise.
* gcc.target/i386/interrupt-16.c: Likewise.
* gcc.target/i386/interrupt-17.c: Likewise.
* gcc.target/i386/interrupt-8.c: Likewise.
* gcc.target/i386/cet-sjlj-6a.c: Combine patterns from
previous change.
* gcc.target/i386/cet-sjlj-6b.c: Likewise.
* gcc.target/i386/pad-10.c: Accept insns in get_pc_thunk.
* gcc.target/i386/pr70321.c: Likewise.
* gcc.target/i386/pr81563.c: Likewise.
* gcc.target/i386/pr84278.c: Likewise.
* gcc.target/i386/pr90773-2.c: Likewise, plus extra loads from
the GOT.
* gcc.target/i386/pr90773-3.c: Likewise.
* gcc.target/i386/pr94913-2.c: Accept additional PIC insns.
* gcc.target/i386/stack-check-17.c: Likewise.
* gcc.target/i386/stack-check-12.c: Do not require dummy stack
probing obviated with PIC.
* gcc.target/i386/pr95126-m32-1.c: Expect missed optimization
with PIC.
* gcc.target/i386/pr95126-m32-2.c: Likewise.
* gcc.target/i386/pr95852-2.c: Accept different optimization
with PIC.
* gcc.target/i386/pr95852-4.c: Likewise.
The following testcase is miscompiled on x86_64-linux.
The problem is in the noce_convert_multiple_sets optimization.
We essentially have:
if (g == 1)
{
g = 1;
f = 23;
}
else
{
g = 2;
f = 20;
}
and for each insn try to create a conditional move sequence.
There is code to detect overlap with the regs used in the condition
and the destinations, so we actually try to construct:
tmp_g = g == 1 ? 1 : 2;
f = g == 1 ? 23 : 20;
g = tmp_g;
which is fine. But, we actually try to create two different
conditional move sequences in each case, seq1 with the whole
(eq (reg/v:HI 82 [ g ]) (const_int 1 [0x1]))
condition and seq2 with cc_cmp
(eq (reg:CCZ 17 flags) (const_int 0 [0]))
to rely on the earlier present comparison. In each case, we
compare the rtx costs and choose the cheaper sequence (seq1 if both
have the same cost).
The problem is that with the skylake tuning,
tmp_g = g == 1 ? 1 : 2;
is actually expanded as
tmp_g = (g == 1) + 1;
in seq1 (which clobbers (reg 17 flags)) and as a cmov in seq2
(which doesn't). The tuning says both have the same cost, so we
pick seq1. Next we check sequences for
f = g == 1 ? 23 : 20; and here the seq2 cmov is cheaper, but it
uses (reg 17 flags) which has been clobbered earlier.
The following patch fixes that by detecting if we in the chosen
sequence clobber some register mentioned in cc_cmp or rev_cc_cmp,
and if yes, arranges for only seq1 (i.e. sequences that emit the
comparison itself) to be used after that.
2022-08-15 Jakub Jelinek <jakub@redhat.com>
PR rtl-optimization/106590
* ifcvt.cc (check_for_cc_cmp_clobbers): New function.
(noce_convert_multiple_sets_1): If SEQ sets or clobbers any regs
mentioned in cc_cmp or rev_cc_cmp, don't consider seq2 for any
further conditional moves.
* gcc.dg/torture/pr106590.c: New test.
This patch moves the lowering of 128-bit V1TImode shifts and rotations by
constant bit counts to sequences of SSE operations from the RTL expansion
pass to the pre-reload split pass. Postponing this splitting of shifts
and rotates enables (will enable) the TImode equivalents of these operations/
instructions to be considered as candidates by the (TImode) STV pass.
Technically, this patch changes the existing expanders to continue to
lower shifts by variable amounts, but constant operands become RTL
instructions, specified by define_insn_and_split that are triggered by
x86_pre_reload_split. The one minor complication is that logical shifts
by multiples of eight, don't get split, but are handled by existing insn
patterns, such as sse2_ashlv1ti3 and sse2_lshrv1ti3. There should be no
changes in generated code with this patch, which just adjusts the pass
in which transformations get applied.
2022-08-13 Roger Sayle <roger@nextmovesoftware.com>
Uroš Bizjak <ubizjak@gmail.com>
gcc/ChangeLog
* config/i386/predicates.md (const_0_to_255_not_mul_8_operand):
New predicate for values between 0/1 and 255, not multiples of 8.
* config/i386/sse.md (ashlv1ti3): Delay lowering of logical left
shifts by constant bit counts.
(*ashlvti3_internal): New define_insn_and_split that lowers
logical left shifts by constant bit counts, that aren't multiples
of 8, before reload.
(lshrv1ti3): Delay lowering of logical right shifts by constant.
(*lshrv1ti3_internal): New define_insn_and_split that lowers
logical right shifts by constant bit counts, that aren't multiples
of 8, before reload.
(ashrv1ti3):: Delay lowering of arithmetic right shifts by
constant bit counts.
(*ashrv1ti3_internal): New define_insn_and_split that lowers
arithmetic right shifts by constant bit counts before reload.
(rotlv1ti3): Delay lowering of rotate left by constant.
(*rotlv1ti3_internal): New define_insn_and_split that lowers
rotate left by constant bits counts before reload.
(rotrv1ti3): Delay lowering of rotate right by constant.
(*rotrv1ti3_internal): New define_insn_and_split that lowers
rotate right by constant bits counts before reload.
This patch disables Wanalyzer-out-of-bounds for analyzer/torture/pr93451.c
and makes the test case pass when compiled with -m32.
The emitted warning is a true positive but only occurs if
sizeof (long int) is less than sizeof (double). I've already discussed a
similar case with Dave in the context of pr96764.c and we came to the
conclusion that we just disable the checker in such cases.
Committed under the "obvious fix" rule.
gcc/testsuite/ChangeLog:
* gcc.dg/analyzer/torture/pr93451.c:
Disable Wanalyzer-out-of-bounds.
Keef Aragon
Xi Ruoyao
Andrew MacLeod
GCC Administrator
Jason Merrill
Tom Honermann
Martin Liska
Kito Cheng
Richard Biener
Sergei Trofimovich
Jakub Jelinek
Iain Buclaw
Aldy Hernandez
Kewen.Lin
Kewen Lin
Takayuki 'January June' Suwa
David Malcolm
Immad Mir
Roger Sayle
Nathan Sidwell
Marek Polacek
Alexandre Oliva
konglin1
Tim Lange