26 lines
529 B
Systemverilog
26 lines
529 B
Systemverilog
/* verilator lint_off UNOPTFLAT */
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interface rvx0_apb ();
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logic pclk;
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logic prstn;
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logic [31:0] paddr;
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logic pwrite;
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logic penable;
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logic [31:0] pwdata;
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logic psel;
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logic pready;
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logic [31:0] prdata;
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logic pslverr;
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modport master (
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input pready, prdata, pslverr,
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output pclk, prstn, paddr, penable, pwrite, pwdata
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);
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modport slave (
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input pclk, prstn, paddr, pwrite, penable, pwdata, psel,
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output pready, prdata, pslverr
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);
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endinterface
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