53 lines
1.4 KiB
Systemverilog
53 lines
1.4 KiB
Systemverilog
// TODO Zicsr
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module rvx0_csr (
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input wire clk_i,
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input wire rst_i,
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input wire [31:0] mepc_i,
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input wire [31:0] mcause_i,
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input wire [31:0] mtval_i,
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input wire mepc_write_i,
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input wire mcause_write_i,
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input wire mtval_write_i,
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output wire [31:0] misa_o, // Hardwired
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output wire [31:0] mvendorid_o, // Hardwired
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output wire [31:0] marchid_o, // Hardwired
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output wire [31:0] mimpid_o, // Hardwired
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output wire [31:0] mhartid_o, // Hardwired
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output reg [31:0] mstatus_o, // TODO
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output reg [31:0] mstatush_o, // TODO
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output reg [31:0] mtvec_o,
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output reg [31:0] mepc_o,
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output reg [31:0] mcause_o,
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output reg [31:0] mtval_o // TODO
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);
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// Add extensions here :)
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assign misa_o = MISA_MXLEN_32;
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assign mvendorid_o = 0;
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assign marchid_o = 0;
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assign mimpid_o = 0;
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assign mhartid_o = 0;
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always @(posedge clk_i) begin
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if (rst_i) begin
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// TODO set from CPU
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mtvec_o = 'h00020000;
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mepc_o = 0;
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mstatus_o = 0;
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mstatush_o = 0;
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end
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if (mepc_write_i) begin
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mepc_o <= mepc_i;
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end
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if (mcause_write_i) begin
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mcause_o <= mcause_i;
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end
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if (mtval_write_i) begin
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mtval_o <= mtval_i;
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end
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end
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endmodule
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