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rv64: Implement RISC-V support, implement VisionFive2 support #34

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alnyan merged 17 commits from feature/rv64 into master 2025-01-21 17:54:55 +00:00
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alnyan commented 2025-01-21 17:52:34 +00:00
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alnyan added the
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kernel
driver
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riscv64
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alnyan added 16 commits 2025-01-21 17:52:35 +00:00
rv64: boot into upper half 86eb2d3252
rv64: implement M-/S-mode trap stubs f46f3ddc31
rv64: platform init, task switching 20fa34c945
rv64: boot into usermode 8ba37c9762
rv64: riscv plic driver, time accouting 86509e39c1
maint: sync up other archs 2f942e1721
rv64: fix timer clock scale 65b8c0ee67
rv64: smp secondary hart startup 16f580e7af
rv64: add jh7110/starfive visionfive2 support 909980f4eb
rv64: fix smp init in asymmetric systems cfc11c402a
mm: PageBox::into_physical_raw/from_physical_raw 5d27bd6033
xtask: increase default mem for riscv64 8ff0f03989
rv64: implement signal handling 6aa3e7f6be
rv64: relax TLB flushes ca82e25cf6
rv64: implement address space dropping 822d4f891c
doc: add notes on VisionFive 2 boot e0bb98e92a
alnyan added 1 commit 2025-01-21 17:53:45 +00:00
rv64: remove commented out M-mode CSRs 5b1b69e467
alnyan merged commit 5b1b69e467 into master 2025-01-21 17:54:55 +00:00
alnyan deleted branch feature/rv64 2025-01-21 17:54:55 +00:00
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alnyan (Mark Poliakov)
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Reference: alnyan/yggdrasil#34
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