alnyan/yggdrasil
1
0
Fork 0
Code Issues 33 Pull Requests Packages Projects Releases Wiki Activity

rv64: Implement RISC-V support, implement VisionFive2 support #34

Merged
alnyan merged 17 commits from feature/rv64 into master 2025-01-21 19:54:55 +02:00
Conversation 0 Commits 17 Files Changed 95 -1
1 changed files with 0 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files
Showing only changes of commit 65b8c0ee67 - Show all commits

1
kernel/src/arch/riscv64/timer.rs
View File

@ -21,7 +21,6 @@ pub fn handle_interrupt() {
sbi::sbi_set_timer(now.wrapping_add(frequency / TICK_RATE));
if Cpu::local().is_bootstrap() {
let frequency = frequency * 1000;
let last = LAST_TICK.swap(now, Ordering::Release);
if frequency != 0 {
if let Some(delta) = now.checked_sub(last) {