 Eugene Rossokha
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dc7968f92f
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Rename makeRegister to Register
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2025-03-17 23:50:50 +02:00 |
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Eugene Rossokha
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64eae5052e
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Rename Arena.setup to Arena.init
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2025-03-17 23:48:57 +02:00 |
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Eugene Rossokha
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7a1a088cbc
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Use std.BoundedArray instead of FixedVec
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2025-03-17 23:46:23 +02:00 |
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Eugene Rossokha
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883f0db654
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Rename translationLevel to TranslationLevel
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2025-03-17 23:46:23 +02:00 |
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 alnyan
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7305ce220a
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AArch64 basic boot and upper reloc
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2025-03-17 23:05:53 +02:00 |
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Eugene Rossokha
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caec288157
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Restrict the target to .freestanding/.none/supported cpu
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2025-03-17 20:05:33 +02:00 |
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alnyan
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aee04d2510
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Add aarch64 target
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2025-03-17 19:56:43 +02:00 |
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Eugene Rossokha
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1641327f28
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Make arch/riscv64.zig one struct
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2025-03-17 19:15:41 +02:00 |
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alnyan
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c4a80c3378
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Make thread queue per-CPU
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2025-03-17 17:54:51 +02:00 |
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alnyan
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c803a3e2b2
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Implement thread-locals for per-CPU data
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2025-03-17 17:26:40 +02:00 |
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alnyan
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856c7b273e
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Implement S-mode exceptions
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2025-03-17 16:01:12 +02:00 |
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alnyan
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4437a66025
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Basic physical memory management
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2025-03-17 13:36:49 +02:00 |
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alnyan
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aeb5950e56
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Basic thread switching
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2025-03-14 22:16:36 +02:00 |
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alnyan
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bebdb21c4e
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WIP: WIP, WIP
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2025-03-14 13:00:54 +02:00 |
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alnyan
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467e4a944a
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Initial commit
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2025-03-13 18:06:14 +02:00 |
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