 alnyan
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1effc9e76f
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phys: remove comment about merging bitmap/refcounts
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2025-03-24 10:16:54 +02:00 |
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alnyan
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1bc326de6d
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phys: remove struct Page, unused
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2025-03-24 10:16:02 +02:00 |
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alnyan
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bc91b5c07c
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phys: make reserved/available regions operate on PFNs
Use PFNs instead of raw physical addresses for more clarity.
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2025-03-24 10:14:41 +02:00 |
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alnyan
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23bb7bb63e
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lib: implement merge on insert in rangemap
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2025-03-24 09:34:59 +02:00 |
|
 Eugene Rossokha
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0785c424b9
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btree/rangemap: rename .new to .init
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2025-03-24 09:34:59 +02:00 |
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Eugene Rossokha
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0a89436d86
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phys: use a bitmap to track pages, get the refcounters out
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2025-03-22 23:33:53 +02:00 |
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alnyan
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a97d79d8ca
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lib: implement RangeMap/BTree
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2025-03-20 09:59:26 +02:00 |
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alnyan
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734cd7eb0e
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aarch64: feature parity with riscv64
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2025-03-18 22:14:49 +02:00 |
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alnyan
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1a8d842479
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refactor: we're not writing Java here
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2025-03-18 22:14:49 +02:00 |
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alnyan
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d3e44e5067
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sync: Spinlock lock_irqsave() impl
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2025-03-18 22:14:49 +02:00 |
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alnyan
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c0df9d712d
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maint: better arch.zig
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2025-03-18 22:14:49 +02:00 |
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|
alnyan
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f85d04d715
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Add more entries to .gitignore
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2025-03-18 22:14:48 +02:00 |
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alnyan
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32b324b132
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doc: add some documentation on platform-independent modules
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2025-03-18 14:15:05 +02:00 |
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|
alnyan
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500a99832c
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doc: add "docs" step to build.zig
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2025-03-18 14:15:01 +02:00 |
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|
alnyan
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0de39ac75b
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aarch64: implement exception stubs
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2025-03-18 14:14:51 +02:00 |
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|
alnyan
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a668443bea
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dtb: make dtb struct more useful
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2025-03-18 14:14:49 +02:00 |
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|
alnyan
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3f79177839
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aarch64: physical memory setup
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2025-03-18 12:04:50 +02:00 |
|
|
Eugene Rossokha
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dc7968f92f
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Rename makeRegister to Register
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2025-03-17 23:50:50 +02:00 |
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|
Eugene Rossokha
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64eae5052e
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Rename Arena.setup to Arena.init
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2025-03-17 23:48:57 +02:00 |
|
|
Eugene Rossokha
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7a1a088cbc
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Use std.BoundedArray instead of FixedVec
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2025-03-17 23:46:23 +02:00 |
|
|
Eugene Rossokha
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883f0db654
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Rename translationLevel to TranslationLevel
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2025-03-17 23:46:23 +02:00 |
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|
alnyan
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7305ce220a
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AArch64 basic boot and upper reloc
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2025-03-17 23:05:53 +02:00 |
|
|
Eugene Rossokha
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caec288157
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Restrict the target to .freestanding/.none/supported cpu
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2025-03-17 20:05:33 +02:00 |
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|
alnyan
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aee04d2510
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Add aarch64 target
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2025-03-17 19:56:43 +02:00 |
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|
Eugene Rossokha
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1641327f28
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Make arch/riscv64.zig one struct
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2025-03-17 19:15:41 +02:00 |
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|
alnyan
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c4a80c3378
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Make thread queue per-CPU
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2025-03-17 17:54:51 +02:00 |
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|
alnyan
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c803a3e2b2
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Implement thread-locals for per-CPU data
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2025-03-17 17:26:40 +02:00 |
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|
alnyan
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856c7b273e
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Implement S-mode exceptions
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2025-03-17 16:01:12 +02:00 |
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|
alnyan
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4437a66025
|
Basic physical memory management
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2025-03-17 13:36:49 +02:00 |
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|
alnyan
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aeb5950e56
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Basic thread switching
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2025-03-14 22:16:36 +02:00 |
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|
alnyan
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bebdb21c4e
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WIP: WIP, WIP
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2025-03-14 13:00:54 +02:00 |
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|
alnyan
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467e4a944a
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Initial commit
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2025-03-13 18:06:14 +02:00 |
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