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Allow IRQs during early initialization

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This commit is contained in:
Mark
2020-01-28 12:22:17 +02:00
parent 8ef26b4450
commit 043c4e7eff
5 changed files with 12 additions and 11 deletions
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include/sys/amd64/asm/asm_irq.h
+3
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@@ -117,6 +117,7 @@ amd64_irq\n:
.endm
#else
// Externs for C code
extern void amd64_irq0_early();
extern void amd64_irq0();
extern void amd64_irq1();
extern void amd64_irq2();
@@ -138,4 +139,6 @@ extern void amd64_irq15();
extern void amd64_irq_ipi();
extern void amd64_irq_ipi_panic();
#endif
extern void amd64_irq_msi0();
#endif
sys/amd64/hw/irq.c
+1 -3
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@@ -141,8 +141,6 @@ int irq_has_handler(uint8_t gsi) {
return !!handler_list[0].func;
}
extern void amd64_irq_msi0();
int irq_add_msi_handler(irq_handler_func_t handler, void *ctx, uint8_t *vector) {
for (size_t i = 0; i < MSI_MAX_HANDLERS; ++i) {
if (!msi_handlers[i].func) {
@@ -171,7 +169,7 @@ void amd64_msi_handle(uint64_t vector) {
void irq_init(int cpu) {
// Special entry
amd64_idt_set(cpu, 32, (uintptr_t) amd64_irq0, 0x08, IDT_FLG_P | IDT_FLG_R0 | IDT_FLG_INT32);
amd64_idt_set(cpu, 32, (uintptr_t) amd64_irq0_early, 0x08, IDT_FLG_P | IDT_FLG_R0 | IDT_FLG_INT32);
amd64_idt_set(cpu, 33, (uintptr_t) amd64_irq1, 0x08, IDT_FLG_P | IDT_FLG_R0 | IDT_FLG_INT32);
amd64_idt_set(cpu, 34, (uintptr_t) amd64_irq2, 0x08, IDT_FLG_P | IDT_FLG_R0 | IDT_FLG_INT32);
sys/amd64/hw/irq0.S
+2 -2
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@@ -3,9 +3,9 @@
.section .text
.global amd64_irq0
.global amd64_irq2_counting
.global amd64_irq0_dummy
.global amd64_irq0_early
amd64_irq0_dummy:
amd64_irq0_early:
cli
pushq %rax
irq_eoi_lapic 0
sys/amd64/kernel.c
+5 -1
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@@ -1,6 +1,8 @@
#include "sys/debug.h"
#include "sys/amd64/loader/multiboot.h"
#include "sys/amd64/asm/asm_irq.h"
#include "sys/amd64/hw/gdt.h"
#include "sys/amd64/cpu.h"
#include "sys/amd64/hw/vesa.h"
#include "sys/amd64/syscall.h"
#include "sys/amd64/hw/idt.h"
@@ -57,7 +59,6 @@ void kernel_main(struct amd64_loader_data *data) {
pseudo_init();
ps2_register_device();
amd64_acpi_init();
#if defined(VESA_ENABLE)
amd64_vesa_init(multiboot_info);
@@ -100,6 +101,9 @@ void kernel_main(struct amd64_loader_data *data) {
amd64_syscall_init();
// Ready to enter multitasking, disable early timer handler
amd64_idt_set(get_cpu()->processor_id, 32, (uintptr_t) amd64_irq0, 0x08, IDT_FLG_P | IDT_FLG_R0 | IDT_FLG_INT32);
while (1) {
asm ("sti; hlt");
}
sys/amd64/smp/smp.c
+1 -5
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@@ -59,11 +59,6 @@ static void amd64_ap_code_entry(void) {
// Setup IDT for this AP
amd64_idt_init(cpu->processor_id);
// Setup temporary timer IRQ redirection for the AP so we don't enter threading
// too early (when scheduler hasn't at least prepared idle tasks)
extern void amd64_irq0_dummy(void);
amd64_idt_set(cpu->processor_id, 32, (uintptr_t) amd64_irq0_dummy, 0x08, IDT_FLG_P | IDT_FLG_R0 | IDT_FLG_INT32);
// Enable LAPIC.SVR.SoftwareEnable bit
// And set spurious interrupt mapping to 0xFF
LAPIC(LAPIC_REG_SVR) |= (1 << 8) | (0xFF);
@@ -82,6 +77,7 @@ static void amd64_ap_code_entry(void) {
asm volatile ("sti; hlt; cli");
} while (!sched_ready);
// Set a real irq0 to perform context switches
amd64_idt_set(cpu->processor_id, 32, (uintptr_t) amd64_irq0, 0x08, IDT_FLG_P | IDT_FLG_R0 | IDT_FLG_INT32);
while (1) {