Support APX Push2/Pop2
PPX functionality for PUSH/POP is not implemented in this patch and will be implemented separately. gas/ChangeLog: 2023-12-28 Zewei Mo <zewei.mo@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c: (enum i386_error): New unsupported_rsp_register and invalid_src_register_set. (md_assemble): Add handler for unsupported_rsp_register and invalid_src_register_set. (check_APX_operands): Add invalid check for push2/pop2. (match_template): Handle check_APX_operands. * testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2.d: New test. * testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added bad testcases for POP2. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F. * i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_R_0 and EVEX_W_MAP4_FF_R_6 * i386-dis-evex.h: Add REG_EVEX_MAP4_8F. * i386-dis.c (PUSH2_POP2_Fixup): Add special handling for PUSH2/POP2. (get_valid_dis386): Add handler for vector length and address_mode for APX-Push2/Pop2 insn. (nd): define nd as b for EVEX-promoted instrutions. (OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn. * i386-gen.c: Add Push2Pop2 bitfield. * i386-opc.h: Regenerated. * i386-opc.tbl: Regenerated.
This commit is contained in:
Mo, Zewei
Cui, Lili
@@ -250,6 +250,7 @@ enum i386_error
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invalid_vector_register_set,
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invalid_tmm_register_set,
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invalid_dest_and_src_register_set,
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invalid_dest_register_set,
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invalid_pseudo_prefix,
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unsupported_vector_index_register,
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unsupported_broadcast,
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@@ -259,6 +260,7 @@ enum i386_error
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no_default_mask,
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unsupported_rc_sae,
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unsupported_vector_size,
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unsupported_rsp_register,
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internal_error,
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};
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@@ -5511,6 +5513,9 @@ md_assemble (char *line)
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case invalid_dest_and_src_register_set:
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err_msg = _("destination and source registers must be distinct");
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break;
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case invalid_dest_register_set:
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err_msg = _("two dest registers must be distinct");
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break;
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case invalid_pseudo_prefix:
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err_msg = _("rex2 pseudo prefix cannot be used");
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break;
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@@ -5539,6 +5544,9 @@ md_assemble (char *line)
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as_bad (_("vector size above %u required for `%s'"), 128u << vector_size,
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pass1_mnem ? pass1_mnem : insn_name (current_templates.start));
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return;
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case unsupported_rsp_register:
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err_msg = _("'rsp' register cannot be used");
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break;
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case internal_error:
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err_msg = _("internal error");
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break;
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@@ -7175,6 +7183,35 @@ check_EgprOperands (const insn_template *t)
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return 0;
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}
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/* Check if APX operands are valid for the instruction. */
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static bool
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check_APX_operands (const insn_template *t)
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{
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/* Push2* and Pop2* cannot use RSP and Pop2* cannot pop two same registers.
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*/
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switch (t->mnem_off)
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{
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case MN_pop2:
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case MN_pop2p:
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if (register_number (i.op[0].regs) == register_number (i.op[1].regs))
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{
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i.error = invalid_dest_register_set;
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return 1;
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}
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/* fall through */
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case MN_push2:
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case MN_push2p:
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if (register_number (i.op[0].regs) == 4
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|| register_number (i.op[1].regs) == 4)
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{
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i.error = unsupported_rsp_register;
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return 1;
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}
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break;
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}
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return 0;
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}
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/* Helper function for the progress() macro in match_template(). */
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static INLINE enum i386_error progress (enum i386_error new,
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enum i386_error last,
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@@ -7675,6 +7712,13 @@ match_template (char mnem_suffix)
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continue;
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}
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/* Check if APX operands are valid. */
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if (check_APX_operands (t))
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{
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specific_error = progress (i.error);
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continue;
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}
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/* Check whether to use the shorter VEX encoding for certain insns where
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the EVEX encoding comes first in the table. This requires the respective
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AVX-* feature to be explicitly enabled.
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@@ -0,0 +1,5 @@
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.* Assembler messages:
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.*:6: Error: `push2' is only supported in 64-bit mode
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.*:7: Error: `push2p' is only supported in 64-bit mode
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.*:8: Error: `pop2' is only supported in 64-bit mode
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.*:9: Error: `pop2p' is only supported in 64-bit mode
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@@ -0,0 +1,9 @@
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# Check 32bit APX-PUSH2/POP2 instructions
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.allow_index_reg
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.text
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_start:
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push2 %rax, %rbx
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push2p %rax, %rbx
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pop2 %rax, %rbx
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pop2p %rax, %rbx
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@@ -511,6 +511,7 @@ if [gas_32_check] then {
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run_dump_test "sm4-intel"
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run_list_test "pbndkb-inval"
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run_list_test "user_msr-inval"
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run_list_test "apx-push2pop2-inval"
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run_list_test "sg"
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run_dump_test "clzero"
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run_dump_test "invlpgb"
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@@ -34,3 +34,8 @@ Disassembly of section .text:
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[ ]*[a-f0-9]+:[ ]+62 f4 e4[ ]+\(bad\)
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[ ]*[a-f0-9]+:[ ]+08 ff[ ]+.*
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[ ]*[a-f0-9]+:[ ]+04 08[ ]+.*
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[ ]*[a-f0-9]+:[ ]+62 f4 3c[ ]+\(bad\)
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[ ]*[a-f0-9]+:[ ]+08 8f c0 ff ff ff[ ]+or.*
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[ ]*[a-f0-9]+:[ ]+62 74 7c 18 8f c0[ ]+pop2 %rax,\(bad\)
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[ ]*[a-f0-9]+:[ ]+62 d4 3c 18 8f[ ]+\(bad\)
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[ ]*[a-f0-9]+:[ ]+c0[ ]+.*
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@@ -40,3 +40,10 @@ _start:
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#{evex} inc %rax %rbx EVEX.vvvv != 1111 && EVEX.ND = 0.
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.insn EVEX.L0.NP.M4.W1 0xff/0, (%rax,%rcx), %rbx
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# pop2 %rax, %r8 set EVEX.ND=0.
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.insn EVEX.L0.M4.W0 0x8f/0, %rax, %r8
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.byte 0xff, 0xff, 0xff
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# pop2 %rax, %r8 set EVEX.vvvv = 1111.
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.insn EVEX.L0.M4.W0 0x8f, %rax, {rn-sae},%r8
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# pop2 %r8, %r8.
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.insn EVEX.L0.M4.W0 0x8f/0, %r8,{rn-sae}, %r8
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@@ -0,0 +1,42 @@
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#as: --64
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#objdump: -dw -Mintel
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#name: i386 APX-push2pop2 insns (Intel disassembly)
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#source: x86-64-apx-push2pop2.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+rax,rbx
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\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+r8,r17
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\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+r31,r9
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\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+r24,r31
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\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+rax,rbx
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\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+r8,r17
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\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+r31,r9
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\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+r24,r31
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\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+rbx,rax
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\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+r17,r8
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\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+r9,r31
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\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+r31,r24
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\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+rbx,rax
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\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+r17,r8
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\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+r9,r31
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\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+r31,r24
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\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+rax,rbx
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\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+r8,r17
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\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+r31,r9
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\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+r24,r31
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\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+rax,rbx
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\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+r8,r17
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\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+r31,r9
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\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+r24,r31
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\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+rbx,rax
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\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+r17,r8
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\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+r9,r31
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\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+r31,r24
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\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+rbx,rax
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\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+r17,r8
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\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+r9,r31
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\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+r31,r24
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@@ -0,0 +1,13 @@
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.* Assembler messages:
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.*:6: Error: operand size mismatch for `push2'
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.*:7: Error: operand size mismatch for `push2'
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.*:8: Error: 'rsp' register cannot be used for `push2'
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.*:9: Error: 'rsp' register cannot be used for `push2'
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.*:10: Error: operand size mismatch for `push2p'
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.*:11: Error: 'rsp' register cannot be used for `push2p'
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.*:12: Error: operand size mismatch for `pop2'
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.*:13: Error: 'rsp' register cannot be used for `pop2'
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.*:14: Error: 'rsp' register cannot be used for `pop2'
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.*:15: Error: two dest registers must be distinct for `pop2'
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.*:16: Error: 'rsp' register cannot be used for `pop2p'
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.*:17: Error: two dest registers must be distinct for `pop2p'
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@@ -0,0 +1,17 @@
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# Check illegal APX-Push2Pop2 instructions
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.allow_index_reg
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.text
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_start:
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push2 %ax, %bx
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push2 %eax, %ebx
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push2 %rsp, %r17
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push2 %r17, %rsp
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push2p %eax, %ebx
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push2p %rsp, %r17
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pop2 %ax, %bx
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pop2 %rax, %rsp
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pop2 %rsp, %rax
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pop2 %r12, %r12
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pop2p %rax, %rsp
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pop2p %r12, %r12
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@@ -0,0 +1,42 @@
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#as: --64
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#objdump: -dw
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#name: x86_64 APX-push2pop2 insns
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#source: x86-64-apx-push2pop2.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+%rbx,%rax
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\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+%r17,%r8
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\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+%r9,%r31
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\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+%r31,%r24
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\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+%rbx,%rax
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\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+%r17,%r8
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\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+%r9,%r31
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\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+%r31,%r24
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\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+%rax,%rbx
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\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+%r8,%r17
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\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+%r31,%r9
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\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+%r24,%r31
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\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+%rax,%rbx
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\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+%r8,%r17
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\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+%r31,%r9
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\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+%r24,%r31
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\s*[a-f0-9]+:\s*62 f4 7c 18 ff f3\s+push2\s+%rbx,%rax
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\s*[a-f0-9]+:\s*62 fc 3c 18 ff f1\s+push2\s+%r17,%r8
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\s*[a-f0-9]+:\s*62 d4 04 10 ff f1\s+push2\s+%r9,%r31
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\s*[a-f0-9]+:\s*62 dc 3c 10 ff f7\s+push2\s+%r31,%r24
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\s*[a-f0-9]+:\s*62 f4 fc 18 ff f3\s+push2p\s+%rbx,%rax
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\s*[a-f0-9]+:\s*62 fc bc 18 ff f1\s+push2p\s+%r17,%r8
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\s*[a-f0-9]+:\s*62 d4 84 10 ff f1\s+push2p\s+%r9,%r31
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\s*[a-f0-9]+:\s*62 dc bc 10 ff f7\s+push2p\s+%r31,%r24
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\s*[a-f0-9]+:\s*62 f4 64 18 8f c0\s+pop2\s+%rax,%rbx
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\s*[a-f0-9]+:\s*62 d4 74 10 8f c0\s+pop2\s+%r8,%r17
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\s*[a-f0-9]+:\s*62 dc 34 18 8f c7\s+pop2\s+%r31,%r9
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\s*[a-f0-9]+:\s*62 dc 04 10 8f c0\s+pop2\s+%r24,%r31
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\s*[a-f0-9]+:\s*62 f4 e4 18 8f c0\s+pop2p\s+%rax,%rbx
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\s*[a-f0-9]+:\s*62 d4 f4 10 8f c0\s+pop2p\s+%r8,%r17
|
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\s*[a-f0-9]+:\s*62 dc b4 18 8f c7\s+pop2p\s+%r31,%r9
|
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\s*[a-f0-9]+:\s*62 dc 84 10 8f c0\s+pop2p\s+%r24,%r31
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@@ -0,0 +1,39 @@
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# Check 64bit APX-Push2Pop2 instructions
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.allow_index_reg
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.text
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_start:
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push2 %rbx, %rax
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push2 %r17, %r8
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push2 %r9, %r31
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push2 %r31, %r24
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push2p %rbx, %rax
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push2p %r17, %r8
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push2p %r9, %r31
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push2p %r31, %r24
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pop2 %rax, %rbx
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pop2 %r8, %r17
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pop2 %r31, %r9
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pop2 %r24, %r31
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pop2p %rax, %rbx
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pop2p %r8, %r17
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pop2p %r31, %r9
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pop2p %r24, %r31
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.intel_syntax noprefix
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push2 rax, rbx
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push2 r8, r17
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push2 r31, r9
|
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push2 r24, r31
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push2p rax, rbx
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push2p r8, r17
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push2p r31, r9
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push2p r24, r31
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pop2 rbx, rax
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pop2 r17, r8
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pop2 r9, r31
|
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pop2 r31, r24
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pop2p rbx, rax
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pop2p r17, r8
|
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pop2p r9, r31
|
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pop2p r31, r24
|
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@@ -345,6 +345,9 @@ run_dump_test "x86-64-avx512dq-rcigrd-intel"
|
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run_dump_test "x86-64-avx512dq-rcigrd"
|
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run_dump_test "x86-64-avx512dq-rcigrne-intel"
|
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run_dump_test "x86-64-avx512dq-rcigrne"
|
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run_dump_test "x86-64-apx-push2pop2"
|
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run_dump_test "x86-64-apx-push2pop2-intel"
|
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run_list_test "x86-64-apx-push2pop2-inval"
|
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run_dump_test "x86-64-avx512dq-rcigru-intel"
|
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run_dump_test "x86-64-avx512dq-rcigru"
|
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run_dump_test "x86-64-avx512dq-rcigrz-intel"
|
||||
|
||||
@@ -79,6 +79,10 @@
|
||||
{ "subQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
||||
{ "xorQ", { VexGv, Ev, sIb }, PREFIX_NP_OR_DATA },
|
||||
},
|
||||
/* REG_EVEX_MAP4_8F */
|
||||
{
|
||||
{ VEX_W_TABLE (EVEX_W_MAP4_8F_R_0) },
|
||||
},
|
||||
/* REG_EVEX_MAP4_F6 */
|
||||
{
|
||||
{ Bad_Opcode },
|
||||
@@ -102,4 +106,9 @@
|
||||
{
|
||||
{ "incQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ "decQ", { VexGv, Ev }, PREFIX_NP_OR_DATA },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ VEX_W_TABLE (EVEX_W_MAP4_FF_R_6) },
|
||||
},
|
||||
|
||||
@@ -442,6 +442,16 @@
|
||||
{ Bad_Opcode },
|
||||
{ "vpshrdw", { XM, Vex, EXx, Ib }, 0 },
|
||||
},
|
||||
/* EVEX_W_MAP4_8F_R_0 */
|
||||
{
|
||||
{ "pop2", { { PUSH2_POP2_Fixup, q_mode}, Eq }, NO_PREFIX },
|
||||
{ "pop2p", { { PUSH2_POP2_Fixup, q_mode}, Eq }, NO_PREFIX },
|
||||
},
|
||||
/* EVEX_W_MAP4_FF_R_6 */
|
||||
{
|
||||
{ "push2", { { PUSH2_POP2_Fixup, q_mode}, Eq }, 0 },
|
||||
{ "push2p", { { PUSH2_POP2_Fixup, q_mode}, Eq }, 0 },
|
||||
},
|
||||
/* EVEX_W_MAP5_5B_P_0 */
|
||||
{
|
||||
{ "vcvtdq2ph%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
|
||||
|
||||
@@ -1035,7 +1035,7 @@ static const struct dis386 evex_table[][256] = {
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
{ REG_TABLE (REG_EVEX_MAP4_8F) },
|
||||
/* 90 */
|
||||
{ Bad_Opcode },
|
||||
{ Bad_Opcode },
|
||||
|
||||
@@ -105,6 +105,7 @@ static bool FXSAVE_Fixup (instr_info *, int, int);
|
||||
static bool MOVSXD_Fixup (instr_info *, int, int);
|
||||
static bool DistinctDest_Fixup (instr_info *, int, int);
|
||||
static bool PREFETCHI_Fixup (instr_info *, int, int);
|
||||
static bool PUSH2_POP2_Fixup (instr_info *, int, int);
|
||||
|
||||
static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
|
||||
enum disassembler_style,
|
||||
@@ -900,6 +901,7 @@ enum
|
||||
REG_EVEX_MAP4_80,
|
||||
REG_EVEX_MAP4_81,
|
||||
REG_EVEX_MAP4_83,
|
||||
REG_EVEX_MAP4_8F,
|
||||
REG_EVEX_MAP4_F6,
|
||||
REG_EVEX_MAP4_F7,
|
||||
REG_EVEX_MAP4_FE,
|
||||
@@ -1739,6 +1741,9 @@ enum
|
||||
EVEX_W_0F3A70,
|
||||
EVEX_W_0F3A72,
|
||||
|
||||
EVEX_W_MAP4_8F_R_0,
|
||||
EVEX_W_MAP4_FF_R_6,
|
||||
|
||||
EVEX_W_MAP5_5B_P_0,
|
||||
EVEX_W_MAP5_7A_P_3,
|
||||
};
|
||||
@@ -13510,6 +13515,9 @@ OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
|
||||
case b_mode:
|
||||
names = att_names8rex;
|
||||
break;
|
||||
case q_mode:
|
||||
names = att_names64;
|
||||
break;
|
||||
case mask_bd_mode:
|
||||
case mask_mode:
|
||||
if (reg > 0x7)
|
||||
@@ -13894,3 +13902,26 @@ PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
|
||||
|
||||
return OP_M (ins, bytemode, sizeflag);
|
||||
}
|
||||
|
||||
static bool
|
||||
PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag)
|
||||
{
|
||||
if (ins->modrm.mod != 3)
|
||||
return true;
|
||||
|
||||
unsigned int vvvv_reg = ins->vex.register_specifier
|
||||
| (!ins->vex.v << 4);
|
||||
unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0)
|
||||
+ (ins->rex2 & REX_B ? 16 : 0);
|
||||
|
||||
/* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers. */
|
||||
if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4
|
||||
|| (!ins->modrm.reg
|
||||
&& vvvv_reg == rm_reg))
|
||||
{
|
||||
oappend (ins, "(bad)");
|
||||
return true;
|
||||
}
|
||||
|
||||
return OP_VEX (ins, bytemode, sizeflag);
|
||||
}
|
||||
|
||||
+1962
-1958
File diff suppressed because it is too large
Load Diff
@@ -3480,3 +3480,12 @@ uwrmsr, 0xf30f38f8, USER_MSR, Modrm|NoSuf|NoRex64, { Reg64, Reg64 }
|
||||
uwrmsr, 0xf3f8/0, USER_MSR, Modrm|Vex128|VexMap7|VexW0|NoSuf, { Imm32, Reg64 }
|
||||
|
||||
// USER_MSR instructions end.
|
||||
|
||||
// APX Push2/Pop2 instructions.
|
||||
|
||||
push2, 0xff/6, APX_F, Modrm|VexW0|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 }
|
||||
push2p, 0xff/6, APX_F, Modrm|VexW1|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 }
|
||||
pop2, 0x8f/0, APX_F, Modrm|VexW0|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 }
|
||||
pop2p, 0x8f/0, APX_F, Modrm|VexW1|EVex128|EVexMap4|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf, { Reg64, Reg64 }
|
||||
|
||||
// APX Push2/Pop2 instructions end.
|
||||
|
||||
+42
-1
@@ -37287,6 +37287,42 @@ static const insn_template i386_optab[] =
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_push2, 0xff, 2, SPACE_EVEXMAP4, 6,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 1, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_push2p, 0xff, 2, SPACE_EVEXMAP4, 6,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 1, 2, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_pop2, 0x8f, 2, SPACE_EVEXMAP4, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 1, 1, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0 } } } },
|
||||
{ MN_pop2p, 0x8f, 2, SPACE_EVEXMAP4, 0,
|
||||
{ 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0,
|
||||
0, 0, 0, 0, 1, 2, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ { 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0 } },
|
||||
{ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } },
|
||||
{ { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0 } },
|
||||
{ { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
|
||||
0, 0, 0, 0, 0, 0 } } } },
|
||||
};
|
||||
|
||||
/* i386 opcode sets table. */
|
||||
@@ -37586,7 +37622,8 @@ static const i386_op_off_t i386_op_sets[] =
|
||||
3842, 3843, 3844, 3845, 3846, 3847, 3848, 3849,
|
||||
3850, 3851, 3852, 3853, 3854, 3855, 3856, 3857,
|
||||
3858, 3859, 3860, 3861, 3862, 3863, 3865, 3867,
|
||||
3869, 3871, 3873, 3874, 3875, 3877, 3879
|
||||
3869, 3871, 3873, 3874, 3875, 3877, 3879, 3880,
|
||||
3881, 3882, 3883
|
||||
};
|
||||
|
||||
/* i386 mnemonics table. */
|
||||
@@ -37624,7 +37661,9 @@ const char i386_mnemonics[] =
|
||||
"\0""vsha512msg2"
|
||||
"\0""vsm3msg2"
|
||||
"\0""sha256msg2"
|
||||
"\0""push2"
|
||||
"\0""fldln2"
|
||||
"\0""pop2"
|
||||
"\0""vsha512rnds2"
|
||||
"\0""vsm3rnds2"
|
||||
"\0""sha256rnds2"
|
||||
@@ -38714,6 +38753,8 @@ const char i386_mnemonics[] =
|
||||
"\0""cqto"
|
||||
"\0""ssto"
|
||||
"\0""cmovo"
|
||||
"\0""push2p"
|
||||
"\0""pop2p"
|
||||
"\0""bswap"
|
||||
"\0""fsubp"
|
||||
"\0""pfrcp"
|
||||
|
||||
Reference in New Issue
Block a user