Support Intel SHA512
gas/ChangeLog: * NEWS: Support Intel SHA512. * config/tc-i386.c: Add sha512. * doc/c-i386.texi: Document .sha512. * testsuite/gas/i386/disassem.d: Add SHA512 tests. * testsuite/gas/i386/disassem.s: Ditto. * testsuite/gas/i386/i386.exp: Run SHA512 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/sha512-intel.d: New test. * testsuite/gas/i386/sha512-inval.l: Ditto. * testsuite/gas/i386/sha512-inval.s: Ditto. * testsuite/gas/i386/sha512.d: Ditto. * testsuite/gas/i386/sha512.s: Ditto. * testsuite/gas/i386/x86-64-sha512-intel.d: Ditto. * testsuite/gas/i386/x86-64-sha512-inval.l: Ditto. * testsuite/gas/i386/x86-64-sha512-inval.s: Ditto. * testsuite/gas/i386/x86-64-sha512.d: Ditto. * testsuite/gas/i386/x86-64-sha512.s: Ditto. opcodes/ChangeLog: * i386-dis.c (Rxmmq): New. (Rymm): Ditto. (PREFIX_VEX_0F38CB): Ditto. (PREFIX_VEX_0F38CC): Ditto. (PREFIX_VEX_0F38CD): Ditto. (VEX_LEN_0F38CB_P_3_W_0): Ditto. (VEX_LEN_0F38CC_P_3_W_0): Ditto. (VEX_LEN_0F38CD_P_3_W_0): Ditto. (VEX_W_0F38CB_P_3): Ditto. (VEX_W_0F38CC_P_3): Ditto. (VEX_W_0F38CD_P_3): Ditto. (prefix_table): Add PREFIX_VEX_0F38CB, PREFIX_VEX_0F38CC, PREFIX_VEX_0F38CD. (vex_len_table): Add VEX_LEN_0F38CB_P_3_W_0, VEX_LEN_0F38CC_P_3_W_0, VEX_LEN_0F38CD_P_3_W_0. (vex_w_table): Add VEX_W_0F38CB_P_3, VEX_W_0F38CC_P_3, VEX_W_0F38CD_P_3. * i386-gen.c (isa_dependencies): Add SHA512. (cpu_flags): Ditto. * i386-init.h: Regenerated. * i386-mnem.h: Ditto. * i386-opc.h (CpuSHA512): New. (i386_cpu_flags): Add cpusha512. * i386-opc.tbl: Add SHA512 instructions. * i386-tbl.h: Regenerated.
This commit is contained in:
Haochen Jiang
@@ -1,5 +1,7 @@
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-*- text -*-
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* Add support for Intel SHA512 instructions.
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* Add support for Intel AVX-VNNI-INT16 instructions.
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Changes in 2.41:
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@@ -1152,6 +1152,7 @@ static const arch_entry cpu_arch[] =
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SUBARCH (fred, FRED, ANY_FRED, false),
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SUBARCH (lkgs, LKGS, ANY_LKGS, false),
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SUBARCH (avx_vnni_int16, AVX_VNNI_INT16, ANY_AVX_VNNI_INT16, false),
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SUBARCH (sha512, SHA512, ANY_SHA512, false),
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};
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#undef SUBARCH
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+2
-1
@@ -208,6 +208,7 @@ accept various extension mnemonics. For example,
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@code{fred},
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@code{lkgs},
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@code{avx_vnni_int16},
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@code{sha512},
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@code{amx_int8},
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@code{amx_bf16},
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@code{amx_fp16},
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@@ -1637,7 +1638,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
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@item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
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@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
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@item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
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@item @samp{.avx_vnni_int16}
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@item @samp{.avx_vnni_int16} @tab @samp{.sha512}
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@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
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@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
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@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
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@@ -345,6 +345,12 @@ Disassembly of section \.text:
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[ ]*[a-f0-9]+:[ ]*c4 e2 01 1c[ ]*\(bad\)
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[ ]*[a-f0-9]+:[ ]*41[ ]*inc[ ]*%ecx
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[ ]*[a-f0-9]+:[ ]*37[ ]*aaa
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[ ]*[a-f0-9]+:[ ]*c4 e2 7f cc[ ]+vsha512msg1[ ]*\(bad\),.*
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[ ]*[a-f0-9]+:[ ]*71 20[ ]+jno.*
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[ ]*[a-f0-9]+:[ ]*c4 e2 7f cd[ ]+vsha512msg2[ ]*\(bad\),.*
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[ ]*[a-f0-9]+:[ ]*71 20[ ]+jno.*
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[ ]*[a-f0-9]+:[ ]*c4 e2 6f cb[ ]+vsha512rnds2[ ]*\(bad\),.*
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[ ]*[a-f0-9]+:[ ]*71 20[ ]+jno.*
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[ ]*[a-f0-9]+:[ ]*62 f2 ad 08 1c[ ]*\(bad\)
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[ ]*[a-f0-9]+:[ ]*01 01[ ]*add[ ]*%eax,\(%ecx\)
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[ ]*[a-f0-9]+:[ ]*62 f3 7d 28 1b[ ]*\(bad\)
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@@ -168,6 +168,9 @@
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.byte 0xC4, 0xE1, 0xF9, 0x93, 0x6F
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.insn VEX.L0.66.0f.W1 0x93, (%edi), %k7
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.byte 0xc4, 0xe2, 0x1, 0x1c, 0x41, 0x37
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.insn VEX.L1.F2.0f38.W0 0xCC, 32(%ecx), %ymm6
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.insn VEX.L1.F2.0f38.W0 0xCD, 32(%ecx), %ymm6
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.insn VEX.L1.F2.0f38.W0 0xCB, 32(%ecx), %ymm2, %ymm6
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.byte 0x62, 0xf2, 0xad, 0x08, 0x1c, 0x01
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.byte 0x1
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.insn EVEX.66.0f3a.W0 0x1b, $0x25, %ymm0, %xmm1
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@@ -498,6 +498,9 @@ if [gas_32_check] then {
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run_list_test "amx-complex-inval"
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run_dump_test "avx-vnni-int16"
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run_dump_test "avx-vnni-int16-intel"
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run_dump_test "sha512"
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run_dump_test "sha512-intel"
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run_list_test "sha512-inval"
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run_list_test "sg"
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run_dump_test "clzero"
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run_dump_test "invlpgb"
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@@ -0,0 +1,15 @@
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#objdump: -dw -Mintel
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#name: i386 SHA512 insns (Intel disassembly)
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#source: sha512.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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\s*[a-f0-9]+:\s*c4 e2 7f cc f5\s+vsha512msg1 ymm6,xmm5
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\s*[a-f0-9]+:\s*c4 e2 7f cd f5\s+vsha512msg2 ymm6,ymm5
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\s*[a-f0-9]+:\s*c4 e2 57 cb f4\s+vsha512rnds2 ymm6,ymm5,xmm4
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\s*[a-f0-9]+:\s*c4 e2 7f cc f5\s+vsha512msg1 ymm6,xmm5
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\s*[a-f0-9]+:\s*c4 e2 7f cd f5\s+vsha512msg2 ymm6,ymm5
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\s*[a-f0-9]+:\s*c4 e2 57 cb f4\s+vsha512rnds2 ymm6,ymm5,xmm4
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@@ -0,0 +1,4 @@
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.* Assembler messages:
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.*:5: Error: operand .* mismatch for `vsha512msg1'
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.*:6: Error: operand .* mismatch for `vsha512msg2'
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.*:7: Error: operand .* mismatch for `vsha512rnds2'
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@@ -0,0 +1,7 @@
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# Check Illegal SHA512 instructions
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.text
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_start:
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vsha512msg1 (%ecx), %ymm6
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vsha512msg2 (%ecx), %ymm6
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vsha512rnds2 (%ecx), %ymm5, %ymm6
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@@ -0,0 +1,15 @@
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#objdump: -dw
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#name: i386 SHA512 insns
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#source: sha512.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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\s*[a-f0-9]+:\s*c4 e2 7f cc f5\s+vsha512msg1 %xmm5,%ymm6
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\s*[a-f0-9]+:\s*c4 e2 7f cd f5\s+vsha512msg2 %ymm5,%ymm6
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\s*[a-f0-9]+:\s*c4 e2 57 cb f4\s+vsha512rnds2 %xmm4,%ymm5,%ymm6
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\s*[a-f0-9]+:\s*c4 e2 7f cc f5\s+vsha512msg1 %xmm5,%ymm6
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\s*[a-f0-9]+:\s*c4 e2 7f cd f5\s+vsha512msg2 %ymm5,%ymm6
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\s*[a-f0-9]+:\s*c4 e2 57 cb f4\s+vsha512rnds2 %xmm4,%ymm5,%ymm6
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@@ -0,0 +1,12 @@
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# Check 32bit SHA512 instructions
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.text
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_start:
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vsha512msg1 %xmm5, %ymm6 #SHA512
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vsha512msg2 %ymm5, %ymm6 #SHA512
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vsha512rnds2 %xmm4, %ymm5, %ymm6 #SHA512
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.intel_syntax noprefix
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vsha512msg1 ymm6, xmm5 #SHA512
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vsha512msg2 ymm6, ymm5 #SHA512
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vsha512rnds2 ymm6, ymm5, xmm4 #SHA512
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@@ -0,0 +1,15 @@
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#objdump: -dw -Mintel
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#name: x86_64 SHA512 insns (Intel disassembly)
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#source: x86-64-sha512.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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\s*[a-f0-9]+:\s*c4 c2 7f cc f7\s+vsha512msg1 ymm6,xmm15
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\s*[a-f0-9]+:\s*c4 62 7f cd fd\s+vsha512msg2 ymm15,ymm5
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\s*[a-f0-9]+:\s*c4 62 57 cb f4\s+vsha512rnds2 ymm14,ymm5,xmm4
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\s*[a-f0-9]+:\s*c4 c2 7f cc f7\s+vsha512msg1 ymm6,xmm15
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\s*[a-f0-9]+:\s*c4 62 7f cd fd\s+vsha512msg2 ymm15,ymm5
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\s*[a-f0-9]+:\s*c4 62 57 cb f4\s+vsha512rnds2 ymm14,ymm5,xmm4
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@@ -0,0 +1,4 @@
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.* Assembler messages:
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.*:5: Error: operand .* mismatch for `vsha512msg1'
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.*:6: Error: operand .* mismatch for `vsha512msg2'
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.*:7: Error: operand .* mismatch for `vsha512rnds2'
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@@ -0,0 +1,7 @@
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# Check Illegal SHA512 instructions
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.text
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_start:
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vsha512msg1 (%ecx), %ymm6
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vsha512msg2 (%ecx), %ymm6
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vsha512rnds2 (%ecx), %ymm5, %ymm6
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@@ -0,0 +1,15 @@
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#objdump: -dw
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#name: x86_64 SHA512 insns
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#source: x86-64-sha512.s
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.*: +file format .*
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Disassembly of section \.text:
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0+ <_start>:
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\s*[a-f0-9]+:\s*c4 c2 7f cc f7\s+vsha512msg1 %xmm15,%ymm6
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\s*[a-f0-9]+:\s*c4 62 7f cd fd\s+vsha512msg2 %ymm5,%ymm15
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\s*[a-f0-9]+:\s*c4 62 57 cb f4\s+vsha512rnds2 %xmm4,%ymm5,%ymm14
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\s*[a-f0-9]+:\s*c4 c2 7f cc f7\s+vsha512msg1 %xmm15,%ymm6
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\s*[a-f0-9]+:\s*c4 62 7f cd fd\s+vsha512msg2 %ymm5,%ymm15
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\s*[a-f0-9]+:\s*c4 62 57 cb f4\s+vsha512rnds2 %xmm4,%ymm5,%ymm14
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@@ -0,0 +1,12 @@
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# Check 64bit SHA512 instructions
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.text
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_start:
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vsha512msg1 %xmm15, %ymm6 #SHA512
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vsha512msg2 %ymm5, %ymm15 #SHA512
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vsha512rnds2 %xmm4, %ymm5, %ymm14 #SHA512
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.intel_syntax noprefix
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vsha512msg1 ymm6, xmm15 #SHA512
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vsha512msg2 ymm15, ymm5 #SHA512
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vsha512rnds2 ymm14, ymm5, xmm4 #SHA512
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@@ -441,6 +441,9 @@ run_dump_test "x86-64-lkgs-intel"
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run_list_test "x86-64-lkgs-inval"
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run_dump_test "x86-64-avx-vnni-int16"
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run_dump_test "x86-64-avx-vnni-int16-intel"
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run_dump_test "x86-64-sha512"
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run_dump_test "x86-64-sha512-intel"
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run_list_test "x86-64-sha512-inval"
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run_dump_test "x86-64-clzero"
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run_dump_test "x86-64-mwaitx-bdver4"
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run_list_test "x86-64-mwaitx-reg"
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+68
-3
@@ -530,6 +530,8 @@ fetch_error (const instr_info *ins)
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#define Nq { OP_R, q_mode }
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#define Ux { OP_R, x_mode }
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#define Uxmm { OP_R, xmm_mode }
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#define Rxmmq { OP_R, xmmq_mode }
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#define Rymm { OP_R, ymm_mode }
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#define Rtmm { OP_R, tmm_mode }
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#define EMCq { OP_EMC, q_mode }
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#define MXC { OP_MXC, 0 }
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@@ -1062,6 +1064,9 @@ enum
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PREFIX_VEX_0F38B1_W_0,
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PREFIX_VEX_0F38D2_W_0,
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PREFIX_VEX_0F38D3_W_0,
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PREFIX_VEX_0F38CB,
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PREFIX_VEX_0F38CC,
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PREFIX_VEX_0F38CD,
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PREFIX_VEX_0F38F5_L_0,
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PREFIX_VEX_0F38F6_L_0,
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PREFIX_VEX_0F38F7_L_0,
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@@ -1304,6 +1309,9 @@ enum
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VEX_LEN_0F385C_X86_64,
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VEX_LEN_0F385E_X86_64,
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VEX_LEN_0F386C_X86_64,
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VEX_LEN_0F38CB_P_3_W_0,
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VEX_LEN_0F38CC_P_3_W_0,
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VEX_LEN_0F38CD_P_3_W_0,
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VEX_LEN_0F38DB,
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VEX_LEN_0F38F2,
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VEX_LEN_0F38F3,
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@@ -1471,6 +1479,9 @@ enum
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VEX_W_0F38B1,
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VEX_W_0F38B4,
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VEX_W_0F38B5,
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VEX_W_0F38CB_P_3,
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VEX_W_0F38CC_P_3,
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VEX_W_0F38CD_P_3,
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VEX_W_0F38CF,
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VEX_W_0F38D2,
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VEX_W_0F38D3,
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@@ -3926,6 +3937,30 @@ static const struct dis386 prefix_table[][4] = {
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{ "vpdpwusds", { XM, Vex, EXx }, 0 },
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},
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/* PREFIX_VEX_0F38CB */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (VEX_W_0F38CB_P_3) },
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},
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/* PREFIX_VEX_0F38CC */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (VEX_W_0F38CC_P_3) },
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},
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/* PREFIX_VEX_0F38CD */
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{
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ VEX_W_TABLE (VEX_W_0F38CD_P_3) },
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},
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/* PREFIX_VEX_0F38F5_L_0 */
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{
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{ "bzhiS", { Gdq, Edq, VexGdq }, 0 },
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@@ -6378,9 +6413,9 @@ static const struct dis386 vex_table[][256] = {
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ Bad_Opcode },
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{ PREFIX_TABLE (PREFIX_VEX_0F38CB) },
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{ PREFIX_TABLE (PREFIX_VEX_0F38CC) },
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{ PREFIX_TABLE (PREFIX_VEX_0F38CD) },
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{ Bad_Opcode },
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{ VEX_W_TABLE (VEX_W_0F38CF) },
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/* d0 */
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@@ -6942,6 +6977,24 @@ static const struct dis386 vex_len_table[][2] = {
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{ VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) },
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},
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/* VEX_LEN_0F38CB_P_3_W_0 */
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{
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{ Bad_Opcode },
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{ "vsha512rnds2", { XM, Vex, Rxmmq }, 0 },
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},
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/* VEX_LEN_0F38CC_P_3_W_0 */
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{
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{ Bad_Opcode },
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{ "vsha512msg1", { XM, Rxmmq }, 0 },
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},
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/* VEX_LEN_0F38CD_P_3_W_0 */
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{
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{ Bad_Opcode },
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{ "vsha512msg2", { XM, Rymm }, 0 },
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},
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/* VEX_LEN_0F38DB */
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{
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{ "vaesimc", { XM, EXx }, PREFIX_DATA },
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@@ -7612,6 +7665,18 @@ static const struct dis386 vex_w_table[][2] = {
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{ Bad_Opcode },
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{ "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
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},
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{
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/* VEX_W_0F38CB_P_3 */
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{ VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) },
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},
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{
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/* VEX_W_0F38CC_P_3 */
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{ VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) },
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},
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{
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/* VEX_W_0F38CD_P_3 */
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{ VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) },
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},
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{
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/* VEX_W_0F38CF */
|
||||
{ "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
|
||||
|
||||
@@ -214,6 +214,8 @@ static const dependency isa_dependencies[] =
|
||||
"XSAVE" },
|
||||
{ "SHA",
|
||||
"SSE2" },
|
||||
{ "SHA512",
|
||||
"AVX2" },
|
||||
{ "XSAVES",
|
||||
"XSAVEC" },
|
||||
{ "XSAVEC",
|
||||
@@ -338,6 +340,7 @@ static bitfield cpu_flags[] =
|
||||
BITFIELD (PRFCHW),
|
||||
BITFIELD (SMAP),
|
||||
BITFIELD (SHA),
|
||||
BITFIELD (SHA512),
|
||||
BITFIELD (ClflushOpt),
|
||||
BITFIELD (XSAVES),
|
||||
BITFIELD (XSAVEC),
|
||||
|
||||
+439
-419
File diff suppressed because it is too large
Load Diff
+1976
-1973
File diff suppressed because it is too large
Load Diff
@@ -175,6 +175,8 @@ enum
|
||||
CpuSMAP,
|
||||
/* SHA instructions required. */
|
||||
CpuSHA,
|
||||
/* SHA512 instructions required. */
|
||||
CpuSHA512,
|
||||
/* CLFLUSHOPT instruction required */
|
||||
CpuClflushOpt,
|
||||
/* XSAVES/XRSTORS instruction required */
|
||||
@@ -403,6 +405,7 @@ typedef union i386_cpu_flags
|
||||
unsigned int cpuprfchw:1;
|
||||
unsigned int cpusmap:1;
|
||||
unsigned int cpusha:1;
|
||||
unsigned int cpusha512:1;
|
||||
unsigned int cpuclflushopt:1;
|
||||
unsigned int cpuxsaves:1;
|
||||
unsigned int cpuxsavec:1;
|
||||
|
||||
@@ -2043,6 +2043,14 @@ sha256rnds2, 0xf38cb, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
sha256msg1, 0xf38cc, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
sha256msg2, 0xf38cd, SHA, Modrm|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM }
|
||||
|
||||
// SHA512 instructions.
|
||||
|
||||
vsha512rnds2, 0xf2cb, SHA512, Modrm|Vex256|Space0F38|VexVVVV|VexW0|NoSuf, { RegXMM, RegYMM, RegYMM }
|
||||
vsha512msg1, 0xf2cc, SHA512, Modrm|Vex256|Space0F38|VexW0|NoSuf, { RegXMM, RegYMM }
|
||||
vsha512msg2, 0xf2cd, SHA512, Modrm|Vex256|Space0F38|VexW0|NoSuf, { RegYMM, RegYMM }
|
||||
|
||||
// SHA512 instructions end.
|
||||
|
||||
// VPCLMULQDQ instructions
|
||||
|
||||
vpclmulqdq, 0x6644, VPCLMULQDQ, Modrm|Vex256|Space0F3A|VexWIG|VexVVVV|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
|
||||
|
||||
+4788
-4735
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user