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Support Intel SM3

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gas/ChangeLog:

	* NEWS: Support Intel SM3.
	* config/tc-i386.c: Add sm3.
	* doc/c-i386.texi: Document .sm3.
	* testsuite/gas/i386/i386.exp: Run sm3 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/sm3-intel.d: New test.
	* testsuite/gas/i386/sm3.d: Ditto.
	* testsuite/gas/i386/sm3.s: Ditto.
	* testsuite/gas/i386/x86-64-sm3-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-sm3.d: Ditto.
	* testsuite/gas/i386/x86-64-sm3.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (PREFIX_VEX_0F38DA_W_0): New.
	(VEX_LEN_0F38DA_W_0_P_0): Ditto.
	(VEX_LEN_0F38DA_W_0_P_2): Ditto.
	(VEX_LEN_0F3ADE_W_0): Ditto.
	(VEX_W_0F38DA): Ditto.
	(VEX_W_0F3ADE): Ditto.
	(prefix_table): Add PREFIX_VEX_0F38DA_W_0.
	(vex_len_table): Add VEX_LEN_0F38DA_W_0_P_0,
	VEX_LEN_0F38DA_W_0_P_2, VEX_LEN_0F3ADE_W_0.
	(vex_w_table): Add VEX_W_0F38DA, VEX_W_0F3ADE.
	* i386-gen.c (isa_dependencies): Add SM3.
	(cpu_flags): Ditto.
	* i386-init.h: Regenerated.
	* i386-mnem.h: Ditto.
	* i386-opc.h (CpuSM3): New.
	(i386_cpu_flags): Add cpusm3.
	* i386-opc.tbl: Add SM3 instructions.
	* i386-tbl.h: Regenerated.
This commit is contained in:
Haochen Jiang
2023-07-24 11:09:49 +08:00
parent 3ac2eb9481
commit c55ba32b7a
18 changed files with 7311 additions and 7016 deletions
Download Patch File Download Diff File Expand all files Collapse all files
gas/NEWS
+2
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@@ -1,5 +1,7 @@
-*- text -*-
* Add support for Intel SM3 instructions.
* Add support for Intel SHA512 instructions.
* Add support for Intel AVX-VNNI-INT16 instructions.
gas/config/tc-i386.c
+1
View File
@@ -1153,6 +1153,7 @@ static const arch_entry cpu_arch[] =
SUBARCH (lkgs, LKGS, ANY_LKGS, false),
SUBARCH (avx_vnni_int16, AVX_VNNI_INT16, ANY_AVX_VNNI_INT16, false),
SUBARCH (sha512, SHA512, ANY_SHA512, false),
SUBARCH (sm3, SM3, ANY_SM3, false),
};
#undef SUBARCH
gas/doc/c-i386.texi
+2 -1
View File
@@ -209,6 +209,7 @@ accept various extension mnemonics. For example,
@code{lkgs},
@code{avx_vnni_int16},
@code{sha512},
@code{sm3},
@code{amx_int8},
@code{amx_bf16},
@code{amx_fp16},
@@ -1638,7 +1639,7 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
@item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
@item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
@item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
@item @samp{.avx_vnni_int16} @tab @samp{.sha512}
@item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3}
@item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
@item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
@item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
gas/testsuite/gas/i386/i386.exp
+2
View File
@@ -501,6 +501,8 @@ if [gas_32_check] then {
run_dump_test "sha512"
run_dump_test "sha512-intel"
run_list_test "sha512-inval"
run_dump_test "sm3"
run_dump_test "sm3-intel"
run_list_test "sg"
run_dump_test "clzero"
run_dump_test "invlpgb"
gas/testsuite/gas/i386/sm3-intel.d
+27
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@@ -0,0 +1,27 @@
#objdump: -dw -Mintel
#name: i386 SM3 insns (Intel disassembly)
#source: sm3.s
.*: +file format .*
Disassembly of section \.text:
0+ <_start>:
\s*[a-f0-9]+:\s*c4 e2 50 da f4\s+vsm3msg1 xmm6,xmm5,xmm4
\s*[a-f0-9]+:\s*c4 e2 50 da b4 f4 00 00 00 10\s+vsm3msg1 xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
\s*[a-f0-9]+:\s*c4 e2 50 da 31\s+vsm3msg1 xmm6,xmm5,XMMWORD PTR \[ecx\]
\s*[a-f0-9]+:\s*c4 e2 51 da f4\s+vsm3msg2 xmm6,xmm5,xmm4
\s*[a-f0-9]+:\s*c4 e2 51 da b4 f4 00 00 00 10\s+vsm3msg2 xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
\s*[a-f0-9]+:\s*c4 e2 51 da 31\s+vsm3msg2 xmm6,xmm5,XMMWORD PTR \[ecx\]
\s*[a-f0-9]+:\s*c4 e3 51 de f4 7b\s+vsm3rnds2 xmm6,xmm5,xmm4,0x7b
\s*[a-f0-9]+:\s*c4 e3 51 de b4 f4 00 00 00 10 7b\s+vsm3rnds2 xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\],0x7b
\s*[a-f0-9]+:\s*c4 e3 51 de 31 7b\s+vsm3rnds2 xmm6,xmm5,XMMWORD PTR \[ecx\],0x7b
\s*[a-f0-9]+:\s*c4 e2 50 da f4\s+vsm3msg1 xmm6,xmm5,xmm4
\s*[a-f0-9]+:\s*c4 e2 50 da b4 f4 00 00 00 10\s+vsm3msg1 xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
\s*[a-f0-9]+:\s*c4 e2 50 da 31\s+vsm3msg1 xmm6,xmm5,XMMWORD PTR \[ecx\]
\s*[a-f0-9]+:\s*c4 e2 51 da f4\s+vsm3msg2 xmm6,xmm5,xmm4
\s*[a-f0-9]+:\s*c4 e2 51 da b4 f4 00 00 00 10\s+vsm3msg2 xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\]
\s*[a-f0-9]+:\s*c4 e2 51 da 31\s+vsm3msg2 xmm6,xmm5,XMMWORD PTR \[ecx\]
\s*[a-f0-9]+:\s*c4 e3 51 de f4 7b\s+vsm3rnds2 xmm6,xmm5,xmm4,0x7b
\s*[a-f0-9]+:\s*c4 e3 51 de b4 f4 00 00 00 10 7b\s+vsm3rnds2 xmm6,xmm5,XMMWORD PTR \[esp\+esi\*8\+0x10000000\],0x7b
\s*[a-f0-9]+:\s*c4 e3 51 de 31 7b\s+vsm3rnds2 xmm6,xmm5,XMMWORD PTR \[ecx\],0x7b
gas/testsuite/gas/i386/sm3.d
+27
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@@ -0,0 +1,27 @@
#objdump: -dw
#name: i386 SM3 insns
#source: sm3.s
.*: +file format .*
Disassembly of section \.text:
0+ <_start>:
\s*[a-f0-9]+:\s*c4 e2 50 da f4\s+vsm3msg1 %xmm4,%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e2 50 da b4 f4 00 00 00 10\s+vsm3msg1 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e2 50 da 31\s+vsm3msg1 \(%ecx\),%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e2 51 da f4\s+vsm3msg2 %xmm4,%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e2 51 da b4 f4 00 00 00 10\s+vsm3msg2 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e2 51 da 31\s+vsm3msg2 \(%ecx\),%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e3 51 de f4 7b\s+vsm3rnds2 \$0x7b,%xmm4,%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e3 51 de b4 f4 00 00 00 10 7b\s+vsm3rnds2 \$0x7b,0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e3 51 de 31 7b\s+vsm3rnds2 \$0x7b,\(%ecx\),%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e2 50 da f4\s+vsm3msg1 %xmm4,%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e2 50 da b4 f4 00 00 00 10\s+vsm3msg1 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e2 50 da 31\s+vsm3msg1 \(%ecx\),%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e2 51 da f4\s+vsm3msg2 %xmm4,%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e2 51 da b4 f4 00 00 00 10\s+vsm3msg2 0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e2 51 da 31\s+vsm3msg2 \(%ecx\),%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e3 51 de f4 7b\s+vsm3rnds2 \$0x7b,%xmm4,%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e3 51 de b4 f4 00 00 00 10 7b\s+vsm3rnds2 \$0x7b,0x10000000\(%esp,%esi,8\),%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 e3 51 de 31 7b\s+vsm3rnds2 \$0x7b,\(%ecx\),%xmm5,%xmm6
gas/testsuite/gas/i386/sm3.s
+24
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@@ -0,0 +1,24 @@
# Check 32bit SM3 instructions
.text
_start:
vsm3msg1 %xmm4, %xmm5, %xmm6 #SM3
vsm3msg1 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #SM3
vsm3msg1 (%ecx), %xmm5, %xmm6 #SM3
vsm3msg2 %xmm4, %xmm5, %xmm6 #SM3
vsm3msg2 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #SM3
vsm3msg2 (%ecx), %xmm5, %xmm6 #SM3
vsm3rnds2 $123, %xmm4, %xmm5, %xmm6 #SM3
vsm3rnds2 $123, 0x10000000(%esp, %esi, 8), %xmm5, %xmm6 #SM3
vsm3rnds2 $123, (%ecx), %xmm5, %xmm6 #SM3
.intel_syntax noprefix
vsm3msg1 xmm6, xmm5, xmm4 #SM3
vsm3msg1 xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #SM3
vsm3msg1 xmm6, xmm5, XMMWORD PTR [ecx] #SM3
vsm3msg2 xmm6, xmm5, xmm4 #SM3
vsm3msg2 xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000] #SM3
vsm3msg2 xmm6, xmm5, XMMWORD PTR [ecx] #SM3
vsm3rnds2 xmm6, xmm5, xmm4, 123 #SM3
vsm3rnds2 xmm6, xmm5, XMMWORD PTR [esp+esi*8+0x10000000], 123 #SM3
vsm3rnds2 xmm6, xmm5, XMMWORD PTR [ecx], 123 #SM3
gas/testsuite/gas/i386/x86-64-sm3-intel.d
+27
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@@ -0,0 +1,27 @@
#objdump: -dw -Mintel
#name: x86_64 SM3 insns (Intel disassembly)
#source: x86-64-sm3.s
.*: +file format .*
Disassembly of section \.text:
0+ <_start>:
\s*[a-f0-9]+:\s*c4 c2 50 da f6\s+vsm3msg1 xmm6,xmm5,xmm14
\s*[a-f0-9]+:\s*c4 a2 00 da b4 f5 00 00 00 10\s+vsm3msg1 xmm6,xmm15,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
\s*[a-f0-9]+:\s*c4 c2 00 da 31\s+vsm3msg1 xmm6,xmm15,XMMWORD PTR \[r9\]
\s*[a-f0-9]+:\s*c4 c2 51 da f6\s+vsm3msg2 xmm6,xmm5,xmm14
\s*[a-f0-9]+:\s*c4 a2 01 da b4 f5 00 00 00 10\s+vsm3msg2 xmm6,xmm15,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
\s*[a-f0-9]+:\s*c4 c2 01 da 31\s+vsm3msg2 xmm6,xmm15,XMMWORD PTR \[r9\]
\s*[a-f0-9]+:\s*c4 c3 51 de f6 7b\s+vsm3rnds2 xmm6,xmm5,xmm14,0x7b
\s*[a-f0-9]+:\s*c4 a3 01 de b4 f5 00 00 00 10 7b\s+vsm3rnds2 xmm6,xmm15,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\],0x7b
\s*[a-f0-9]+:\s*c4 c3 01 de 31 7b\s+vsm3rnds2 xmm6,xmm15,XMMWORD PTR \[r9\],0x7b
\s*[a-f0-9]+:\s*c4 c2 50 da f6\s+vsm3msg1 xmm6,xmm5,xmm14
\s*[a-f0-9]+:\s*c4 a2 00 da b4 f5 00 00 00 10\s+vsm3msg1 xmm6,xmm15,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
\s*[a-f0-9]+:\s*c4 c2 00 da 31\s+vsm3msg1 xmm6,xmm15,XMMWORD PTR \[r9\]
\s*[a-f0-9]+:\s*c4 c2 51 da f6\s+vsm3msg2 xmm6,xmm5,xmm14
\s*[a-f0-9]+:\s*c4 a2 01 da b4 f5 00 00 00 10\s+vsm3msg2 xmm6,xmm15,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\]
\s*[a-f0-9]+:\s*c4 c2 01 da 31\s+vsm3msg2 xmm6,xmm15,XMMWORD PTR \[r9\]
\s*[a-f0-9]+:\s*c4 c3 51 de f6 7b\s+vsm3rnds2 xmm6,xmm5,xmm14,0x7b
\s*[a-f0-9]+:\s*c4 a3 01 de b4 f5 00 00 00 10 7b\s+vsm3rnds2 xmm6,xmm15,XMMWORD PTR \[rbp\+r14\*8\+0x10000000\],0x7b
\s*[a-f0-9]+:\s*c4 c3 01 de 31 7b\s+vsm3rnds2 xmm6,xmm15,XMMWORD PTR \[r9\],0x7b
gas/testsuite/gas/i386/x86-64-sm3.d
+27
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@@ -0,0 +1,27 @@
#objdump: -dw
#name: x86_64 SM3 insns
#source: x86-64-sm3.s
.*: +file format .*
Disassembly of section \.text:
0+ <_start>:
\s*[a-f0-9]+:\s*c4 c2 50 da f6\s+vsm3msg1 %xmm14,%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 a2 00 da b4 f5 00 00 00 10\s+vsm3msg1 0x10000000\(%rbp,%r14,8\),%xmm15,%xmm6
\s*[a-f0-9]+:\s*c4 c2 00 da 31\s+vsm3msg1 \(%r9\),%xmm15,%xmm6
\s*[a-f0-9]+:\s*c4 c2 51 da f6\s+vsm3msg2 %xmm14,%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 a2 01 da b4 f5 00 00 00 10\s+vsm3msg2 0x10000000\(%rbp,%r14,8\),%xmm15,%xmm6
\s*[a-f0-9]+:\s*c4 c2 01 da 31\s+vsm3msg2 \(%r9\),%xmm15,%xmm6
\s*[a-f0-9]+:\s*c4 c3 51 de f6 7b\s+vsm3rnds2 \$0x7b,%xmm14,%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 a3 01 de b4 f5 00 00 00 10 7b\s+vsm3rnds2 \$0x7b,0x10000000\(%rbp,%r14,8\),%xmm15,%xmm6
\s*[a-f0-9]+:\s*c4 c3 01 de 31 7b\s+vsm3rnds2 \$0x7b,\(%r9\),%xmm15,%xmm6
\s*[a-f0-9]+:\s*c4 c2 50 da f6\s+vsm3msg1 %xmm14,%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 a2 00 da b4 f5 00 00 00 10\s+vsm3msg1 0x10000000\(%rbp,%r14,8\),%xmm15,%xmm6
\s*[a-f0-9]+:\s*c4 c2 00 da 31\s+vsm3msg1 \(%r9\),%xmm15,%xmm6
\s*[a-f0-9]+:\s*c4 c2 51 da f6\s+vsm3msg2 %xmm14,%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 a2 01 da b4 f5 00 00 00 10\s+vsm3msg2 0x10000000\(%rbp,%r14,8\),%xmm15,%xmm6
\s*[a-f0-9]+:\s*c4 c2 01 da 31\s+vsm3msg2 \(%r9\),%xmm15,%xmm6
\s*[a-f0-9]+:\s*c4 c3 51 de f6 7b\s+vsm3rnds2 \$0x7b,%xmm14,%xmm5,%xmm6
\s*[a-f0-9]+:\s*c4 a3 01 de b4 f5 00 00 00 10 7b\s+vsm3rnds2 \$0x7b,0x10000000\(%rbp,%r14,8\),%xmm15,%xmm6
\s*[a-f0-9]+:\s*c4 c3 01 de 31 7b\s+vsm3rnds2 \$0x7b,\(%r9\),%xmm15,%xmm6
gas/testsuite/gas/i386/x86-64-sm3.s
+24
View File
@@ -0,0 +1,24 @@
# Check 64bit SM3 instructions
.text
_start:
vsm3msg1 %xmm14, %xmm5, %xmm6 #SM3
vsm3msg1 0x10000000(%rbp, %r14, 8), %xmm15, %xmm6 #SM3
vsm3msg1 (%r9), %xmm15, %xmm6 #SM3
vsm3msg2 %xmm14, %xmm5, %xmm6 #SM3
vsm3msg2 0x10000000(%rbp, %r14, 8), %xmm15, %xmm6 #SM3
vsm3msg2 (%r9), %xmm15, %xmm6 #SM3
vsm3rnds2 $123, %xmm14, %xmm5, %xmm6 #SM3
vsm3rnds2 $123, 0x10000000(%rbp, %r14, 8), %xmm15, %xmm6 #SM3
vsm3rnds2 $123, (%r9), %xmm15, %xmm6 #SM3
.intel_syntax noprefix
vsm3msg1 xmm6, xmm5, xmm14 #SM3
vsm3msg1 xmm6, xmm15, XMMWORD PTR [rbp+r14*8+0x10000000] #SM3
vsm3msg1 xmm6, xmm15, XMMWORD PTR [r9] #SM3
vsm3msg2 xmm6, xmm5, xmm14 #SM3
vsm3msg2 xmm6, xmm15, XMMWORD PTR [rbp+r14*8+0x10000000] #SM3
vsm3msg2 xmm6, xmm15, XMMWORD PTR [r9] #SM3
vsm3rnds2 xmm6, xmm5, xmm14, 123 #SM3
vsm3rnds2 xmm6, xmm15, XMMWORD PTR [rbp+r14*8+0x10000000], 123 #SM3
vsm3rnds2 xmm6, xmm15, XMMWORD PTR [r9], 123 #SM3
gas/testsuite/gas/i386/x86-64.exp
+2
View File
@@ -444,6 +444,8 @@ run_dump_test "x86-64-avx-vnni-int16-intel"
run_dump_test "x86-64-sha512"
run_dump_test "x86-64-sha512-intel"
run_list_test "x86-64-sha512-inval"
run_dump_test "x86-64-sm3"
run_dump_test "x86-64-sm3-intel"
run_dump_test "x86-64-clzero"
run_dump_test "x86-64-mwaitx-bdver4"
run_list_test "x86-64-mwaitx-reg"
opcodes/i386-dis.c
+38 -2
View File
@@ -1067,6 +1067,7 @@ enum
PREFIX_VEX_0F38CB,
PREFIX_VEX_0F38CC,
PREFIX_VEX_0F38CD,
PREFIX_VEX_0F38DA_W_0,
PREFIX_VEX_0F38F5_L_0,
PREFIX_VEX_0F38F6_L_0,
PREFIX_VEX_0F38F7_L_0,
@@ -1312,6 +1313,8 @@ enum
VEX_LEN_0F38CB_P_3_W_0,
VEX_LEN_0F38CC_P_3_W_0,
VEX_LEN_0F38CD_P_3_W_0,
VEX_LEN_0F38DA_W_0_P_0,
VEX_LEN_0F38DA_W_0_P_2,
VEX_LEN_0F38DB,
VEX_LEN_0F38F2,
VEX_LEN_0F38F3,
@@ -1342,6 +1345,7 @@ enum
VEX_LEN_0F3A61,
VEX_LEN_0F3A62,
VEX_LEN_0F3A63,
VEX_LEN_0F3ADE_W_0,
VEX_LEN_0F3ADF,
VEX_LEN_0F3AF0,
VEX_LEN_XOP_08_85,
@@ -1485,6 +1489,7 @@ enum
VEX_W_0F38CF,
VEX_W_0F38D2,
VEX_W_0F38D3,
VEX_W_0F38DA,
VEX_W_0F3A00_L_1,
VEX_W_0F3A01_L_1,
VEX_W_0F3A02,
@@ -1502,6 +1507,7 @@ enum
VEX_W_0F3A4C,
VEX_W_0F3ACE,
VEX_W_0F3ACF,
VEX_W_0F3ADE,
VEX_W_XOP_08_85_L_0,
VEX_W_XOP_08_86_L_0,
@@ -3961,6 +3967,13 @@ static const struct dis386 prefix_table[][4] = {
{ VEX_W_TABLE (VEX_W_0F38CD_P_3) },
},
/* PREFIX_VEX_0F38DA_W_0 */
{
{ VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) },
{ Bad_Opcode },
{ VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) },
},
/* PREFIX_VEX_0F38F5_L_0 */
{
{ "bzhiS", { Gdq, Edq, VexGdq }, 0 },
@@ -6430,7 +6443,7 @@ static const struct dis386 vex_table[][256] = {
/* d8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ VEX_W_TABLE (VEX_W_0F38DA) },
{ VEX_LEN_TABLE (VEX_LEN_0F38DB) },
{ "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
{ "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
@@ -6725,7 +6738,7 @@ static const struct dis386 vex_table[][256] = {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ VEX_W_TABLE (VEX_W_0F3ADE) },
{ VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
/* e0 */
{ Bad_Opcode },
@@ -6995,6 +7008,16 @@ static const struct dis386 vex_len_table[][2] = {
{ "vsha512msg2", { XM, Rymm }, 0 },
},
/* VEX_LEN_0F38DA_W_0_P_0 */
{
{ "vsm3msg1", { XM, Vex, EXxmm }, 0 },
},
/* VEX_LEN_0F38DA_W_0_P_2 */
{
{ "vsm3msg2", { XM, Vex, EXxmm }, 0 },
},
/* VEX_LEN_0F38DB */
{
{ "vaesimc", { XM, EXx }, PREFIX_DATA },
@@ -7153,6 +7176,11 @@ static const struct dis386 vex_len_table[][2] = {
{ "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0F3ADE_W_0 */
{
{ "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
},
/* VEX_LEN_0F3ADF */
{
{ "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
@@ -7689,6 +7717,10 @@ static const struct dis386 vex_w_table[][2] = {
/* VEX_W_0F38D3 */
{ PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) },
},
{
/* VEX_W_0F38DA */
{ PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) },
},
{
/* VEX_W_0F3A00_L_1 */
{ Bad_Opcode },
@@ -7761,6 +7793,10 @@ static const struct dis386 vex_w_table[][2] = {
{ Bad_Opcode },
{ "%XEvgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
},
{
/* VEX_W_0F3ADE */
{ VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
},
/* VEX_W_XOP_08_85_L_0 */
{
{ "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
opcodes/i386-gen.c
+3
View File
@@ -216,6 +216,8 @@ static const dependency isa_dependencies[] =
"SSE2" },
{ "SHA512",
"AVX2" },
{ "SM3",
"AVX" },
{ "XSAVES",
"XSAVEC" },
{ "XSAVEC",
@@ -341,6 +343,7 @@ static bitfield cpu_flags[] =
BITFIELD (SMAP),
BITFIELD (SHA),
BITFIELD (SHA512),
BITFIELD (SM3),
BITFIELD (ClflushOpt),
BITFIELD (XSAVES),
BITFIELD (XSAVEC),
opcodes/i386-init.h
+440 -420
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File diff suppressed because it is too large Load Diff
opcodes/i386-mnem.h
+1978 -1975
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File diff suppressed because it is too large Load Diff
opcodes/i386-opc.h
+3
View File
@@ -177,6 +177,8 @@ enum
CpuSHA,
/* SHA512 instructions required. */
CpuSHA512,
/* SM3 instructions required. */
CpuSM3,
/* CLFLUSHOPT instruction required */
CpuClflushOpt,
/* XSAVES/XRSTORS instruction required */
@@ -406,6 +408,7 @@ typedef union i386_cpu_flags
unsigned int cpusmap:1;
unsigned int cpusha:1;
unsigned int cpusha512:1;
unsigned int cpusm3:1;
unsigned int cpuclflushopt:1;
unsigned int cpuxsaves:1;
unsigned int cpuxsavec:1;
opcodes/i386-opc.tbl
+7
View File
@@ -2051,6 +2051,13 @@ vsha512msg2, 0xf2cd, SHA512, Modrm|Vex256|Space0F38|VexW0|NoSuf, { RegYMM, RegYM
// SHA512 instructions end.
// SM3 instructions.
vsm3rnds2, 0x66de, SM3, Modrm|Space0F3A|Vex128|VexVVVV|VexW0|NoSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vsm3msg1, 0xda, SM3, Modrm|Space0F38|Vex128|VexVVVV|VexW0|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
vsm3msg2, 0x66da, SM3, Modrm|Space0F38|Vex128|VexVVVV|VexW0|NoSuf, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM }
// SM3 instructions end.
// VPCLMULQDQ instructions
vpclmulqdq, 0x6644, VPCLMULQDQ, Modrm|Vex256|Space0F3A|VexWIG|VexVVVV|NoSuf, { Imm8|Imm8S, Unspecified|BaseIndex|RegYMM, RegYMM, RegYMM }
opcodes/i386-tbl.h
+4677 -4618
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File diff suppressed because it is too large Load Diff