The ELF psABI-s are quite clear here: On 32-bit the data type is 12
bytes long (with 2 bytes of trailing padding), while on 64-bit it is 16
bytes long (with 6 bytes of padding). Make ieee_md_atof() capable of
handling such padding, and specify the needed padding for x86 (leaving
non-ELF targets alone for now). Split the existing x86 testcase.
* dwarf2dbg.c (get_directory_table_entry): Ensure that dir[0]
contains current working directory.
(out_dir_and_file_list): Likewise.
* testsuite/gas/elf/dwarf-5-dir0.s: New test source file.
* testsuite/gas/elf/dwarf-5-dir0.d: New test driver.
* testsuite/gas/elf/elf.exp: Run the new test.
* testsuite/gas/elf/dwarf-5-file0.d: Adjust expected output.
* testsuite/gas/i386/dwarf5-line-1.d: Likewise.
* testsuite/gas/i386/dwarf5-line-2.d: Likewise.
Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits
in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32
in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx).
There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8
operands predated our current conventions; those instructions moved to map 3.
FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3
is very sparsely populated. Most of the FP16 instructions share opcodes and
prefix (EVEX.pp) bits with the related FP32 operations.
Intel AVX512 FP16 instructions has new displacements scaling rules, please refer
to the public software developer manual for detail information.
gas/
2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Wei Xiao <wei3.xiao@intel.com>
Lili Cui <lili.cui@intel.com>
* testsuite/gas/i386/i386.exp: Run FP16 tests.
* testsuite/gas/i386/avx512_fp16-intel.d: New test.
* testsuite/gas/i386/avx512_fp16-inval-bcast.l: Ditto.
* testsuite/gas/i386/avx512_fp16-inval-bcast.s: Ditto.
* testsuite/gas/i386/avx512_fp16.d: Ditto.
* testsuite/gas/i386/avx512_fp16.s: Ditto.
* testsuite/gas/i386/avx512_fp16_pseudo_ops.d: Ditto.
* testsuite/gas/i386/avx512_fp16_pseudo_ops.s: Ditto.
* testsuite/gas/i386/avx512_fp16_vl-intel.d: Ditto.
* testsuite/gas/i386/avx512_fp16_vl.d: Ditto.
* testsuite/gas/i386/avx512_fp16_vl.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16-inval-bcast.l: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16-inval-bcast.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16_pseudo_ops.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16_pseudo_ops.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16_vl-intel.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16_vl.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16_vl.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16-inval-register.l: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16-inval-register.s: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16-bad.d: Ditto.
* testsuite/gas/i386/x86-64-avx512_fp16-bad.s: Ditto.
* testsuite/gas/i386/x86-64-default-suffix-avx.d: Add new testcase.
* testsuite/gas/i386/x86-64-default-suffix.d: Ditto.
* testsuite/gas/i386/x86-64-default-suffix.s: Ditto.
* testsuite/gas/i386/xmmword.l: Ditto.
* testsuite/gas/i386/xmmword.s: Ditto.
Intel AVX512 FP16 instructions use maps 3, 5 and 6. Maps 5 and 6 use 3 bits
in the EVEX.mmm field (0b101, 0b110). Map 5 is for instructions that were FP32
in map 1 (0Fxx). Map 6 is for instructions that were FP32 in map 2 (0F38xx).
There are some exceptions to this rule. Some things in map 1 (0Fxx) with imm8
operands predated our current conventions; those instructions moved to map 3.
FP32 things in map 3 (0F3Axx) found new opcodes in map3 for FP16 because map3
is very sparsely populated. Most of the FP16 instructions share opcodes and
prefix (EVEX.pp) bits with the related FP32 operations.
Intel AVX512 FP16 instructions has new displacements scaling rules, please refer
to the public software developer manual for detail information.
gas/
2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Wei Xiao <wei3.xiao@intel.com>
Lili Cui <lili.cui@intel.com>
* config/tc-i386.c (struct Broadcast_Operation): Adjust comment.
(cpu_arch): Add .avx512_fp16.
(cpu_noarch): Add noavx512_fp16.
(pte): Add evexmap5 and evexmap6.
(build_evex_prefix): Handle EVEXMAP5 and EVEXMAP6.
(check_VecOperations): Handle {1to32}.
(check_VecOperands): Handle CheckRegNumb.
(check_word_reg): Handle Toqword.
(i386_error): Add invalid_dest_and_src_register_set.
(match_template): Handle invalid_dest_and_src_register_set.
* doc/c-i386.texi: Document avx512_fp16, noavx512_fp16.
opcodes/
2021-08-05 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
H.J. Lu <hongjiu.lu@intel.com>
Wei Xiao <wei3.xiao@intel.com>
Lili Cui <lili.cui@intel.com>
* i386-dis.c (EXwScalarS): New.
(EXxh): Ditto.
(EXxhc): Ditto.
(EXxmmqh): Ditto.
(EXxmmqdh): Ditto.
(EXEvexXwb): Ditto.
(DistinctDest_Fixup): Ditto.
(enum): Add xh_mode, evex_half_bcst_xmmqh_mode, evex_half_bcst_xmmqdh_mode
and w_swap_mode.
(enum): Add PREFIX_EVEX_0F3A08_W_0, PREFIX_EVEX_0F3A0A_W_0,
PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A56,
PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66, PREFIX_EVEX_0F3A67,
PREFIX_EVEX_0F3AC2, PREFIX_EVEX_MAP5_10, PREFIX_EVEX_MAP5_11,
PREFIX_EVEX_MAP5_1D, PREFIX_EVEX_MAP5_2A, PREFIX_EVEX_MAP5_2C,
PREFIX_EVEX_MAP5_2D, PREFIX_EVEX_MAP5_2E, PREFIX_EVEX_MAP5_2F,
PREFIX_EVEX_MAP5_51, PREFIX_EVEX_MAP5_58, PREFIX_EVEX_MAP5_59,
PREFIX_EVEX_MAP5_5A_W_0, PREFIX_EVEX_MAP5_5A_W_1,
PREFIX_EVEX_MAP5_5B_W_0, PREFIX_EVEX_MAP5_5B_W_1,
PREFIX_EVEX_MAP5_5C, PREFIX_EVEX_MAP5_5D, PREFIX_EVEX_MAP5_5E,
PREFIX_EVEX_MAP5_5F, PREFIX_EVEX_MAP5_78, PREFIX_EVEX_MAP5_79,
PREFIX_EVEX_MAP5_7A, PREFIX_EVEX_MAP5_7B, PREFIX_EVEX_MAP5_7C,
PREFIX_EVEX_MAP5_7D_W_0, PREFIX_EVEX_MAP6_13, PREFIX_EVEX_MAP6_56,
PREFIX_EVEX_MAP6_57, PREFIX_EVEX_MAP6_D6, PREFIX_EVEX_MAP6_D7
(enum): Add EVEX_MAP5 and EVEX_MAP6.
(enum): Add EVEX_W_MAP5_5A, EVEX_W_MAP5_5B,
EVEX_W_MAP5_78_P_0, EVEX_W_MAP5_78_P_2, EVEX_W_MAP5_79_P_0,
EVEX_W_MAP5_79_P_2, EVEX_W_MAP5_7A_P_2, EVEX_W_MAP5_7A_P_3,
EVEX_W_MAP5_7B_P_2, EVEX_W_MAP5_7C_P_0, EVEX_W_MAP5_7C_P_2,
EVEX_W_MAP5_7D, EVEX_W_MAP6_13_P_0, EVEX_W_MAP6_13_P_2,
(get_valid_dis386): Properly handle new instructions.
(intel_operand_size): Handle new modes.
(OP_E_memory): Ditto.
(OP_EX): Ditto.
* i386-dis-evex.h: Updated for AVX512_FP16.
* i386-dis-evex-mod.h: Updated for AVX512_FP16.
* i386-dis-evex-prefix.h: Updated for AVX512_FP16.
* i386-dis-evex-reg.h : Updated for AVX512_FP16.
* i386-dis-evex-w.h : Updated for AVX512_FP16.
* i386-gen.c (cpu_flag_init): Add CPU_AVX512_FP16_FLAGS,
and CPU_ANY_AVX512_FP16_FLAGS. Update CPU_ANY_AVX512F_FLAGS
and CPU_ANY_AVX512BW_FLAGS.
(cpu_flags): Add CpuAVX512_FP16.
(opcode_modifiers): Add DistinctDest.
* i386-opc.h (enum): (AVX512_FP16): New.
(i386_opcode_modifier): Add reqdistinctreg.
(i386_cpu_flags): Add cpuavx512_fp16.
(EVEXMAP5): Defined as a macro.
(EVEXMAP6): Ditto.
* i386-opc.tbl: Add Intel AVX512_FP16 instructions.
* i386-init.h: Regenerated.
* i386-tbl.h: Ditto.
opcodes/
* s390-opc.c (INSTR_SIY_RD): New instruction format.
(MASK_SIY_RD): New instruction mask.
* s390-opc.txt: Change instruction format of lpswey to SIY_RD.
gas/
* testsuite/gas/s390/zarch-arch14.d: Remove last operand of
lpswey.
* testsuite/gas/s390/zarch-arch14.s: Likewise.
Global tbss symbols weren't correctly handled and were generating
a symbol with XTY_SD instead of XTY_CM as expected.
gas/
* config/tc-ppc.c (ppc_frog_symbol): Generate a XTY_CM when
a symbol has a storage class of XMC_UL.
Most of the algorithms for XCOFF in tc-ppc.c assume that
the csects field of a ppc_xcoff_section isn't NULL.
This was already made for most of the sections with the creation
of a dummy symbol.
This patch simply mades it default when creating a xcoff_section.
gas/
* config/tc-ppc.c (ppc_init_xcoff_section): Always create
the dummy symbol.
(md_begin): Adjust ppc_init_xcoff_section call.
(ppc_comm): Likewise.
(ppc_change_csect): Likewise.
debug_abbrev doesn't use end_exp to compute its size. However, it must
be NULL. Otherwise, ppc_xcoff_end might try to access uninitialized
memory.
gas/
* config/tc-ppc.c (ppc_dwsect): Use XCNEW instead of XNEW when creating
a new subsection.
A C_BSTAT debug symbol specifies the beginning of a static block.
Its n_value is the index of the csect containing static symbols.
A C_STSYM debug symbol represents the stabstring of a statically
allocated symbol. Its n_value is the offset in the csect pointed
by the containing C_BSTAT.
These two special n_value were not correctly handled both when
generating object files with gas or when reading them with objdump.
This patch tries to improve that and, above all, to allow gas-generated
object files with such symbols to be accepted by AIX ld.
bfd/
* coff-bfd.c (bfd_coff_get_syment): Adjust n_value of symbols
having fix_value = 1 in order to be an index and not a memory
offset.
* coffgen.c (coff_get_symbol_info): Likewize.
(coff_print_symbol): Likewize.
gas/
* config/tc-ppc.c (ppc_frob_label): Don't change within if
already set.
(ppc_stabx): Remove workaround changing exp.X_add_symbol's
within.
* config/tc-ppc.h (struct ppc_tc_sy): Update comments.
* symbols.c (resolve_symbol_value): Remove symbol update
when final_val is 0 and it's an AIX debug symbol.
* testsuite/gas/ppc/aix.exp: Add new tests.
* testsuite/gas/ppc/xcoff-stsym-32.d: New test.
* testsuite/gas/ppc/xcoff-stsym-64.d: New test.
* testsuite/gas/ppc/xcoff-stsym.s: New test.
If any pair of operands in AMX instructions with 3 TMM register operands
are the same, the instruction will UD. Don't call register_number to
check for distinct TMM register operands since all TMM register operands
have the same size.
* config/tc-i386.c (check_VecOperands): Remove register_number
call when checking for distinct TMM register operands.
PowerPC gas and objdump for a long time have allowed certain -m/-M
options that extend a base cpu with extra functional units to be
specified before the base cpu. For example, "-maltivec -mpower4" is
the same as "-mpower4 -maltivec". See
https://sourceware.org/pipermail/binutils/2008-January/054935.html
It doesn't make as much sense that .machine keep any of these
"sticky" flags when handling a new base cpu. See gcc PR101393. I
think that instead .machine ought to override the command line.
That's what this patch does. It is still possible to extend cpu
functionality with .machine. For example the following can be
assembled when selecting a basic -mppc on the command line:
.machine power5
.machine altivec
frin 1,2
lvsr 3,4,5
Here, ".machine altivec" extends the ".machine power5" so that both
the power5 "frin" instruction and the altivec "lvsr" instruction are
enabled. Swapping the two ".machine" directives would result in
failure to assemble "lvsr".
This change will expose some assembly errors, such as the one in
glibc/sysdeps/powerpc/powerpc64/tst-ucontext-ppc64-vscr.c, a file
compiled with -maltivec but containing
asm volatile (".machine push;\n"
".machine \"power5\";\n"
"vspltisb %0,0;\n"
"vspltisb %1,-1;\n"
"vpkuwus %0,%0,%1;\n"
"mfvscr %0;\n"
"stvx %0,0,%2;\n"
".machine pop;"
: "=v" (v0), "=v" (v1)
: "r" (vscr_ptr)
: "memory");
It's just wrong to choose power5 for a bunch of altivec instructions
and in fact all of those .machine directives are unnecessary.
* config/tc-ppc.c (ppc_machine): Don't use command line
sticky options.
While EVEX.L'L are indeed ignored when EVEX.b stands for just SAE,
EVEX.b itself is not ignored when an insn permits neither rounding
control nor SAE.
While changing this aspect of EVEX.b handling, also alter unduly set
embedded broadcast: Don't call BadOp(), screwing up subsequent
disassembly, but emit "{bad}" instead.
Their sole use is for {,V}EXTRACTPS / {,V}P{EXT,INS}RB respectively; for
consistency also limit use of dqw_mode to Jdqw. 64-bit disassembly
reflecting REX.W / VEX.W is not in line with the assembler's opcode
table having NoRex64 / VexWIG in all respective templates, i.e. assembly
input isn't being honored there either. Obviously the 0FC5 encodings of
{,V}PEXTRW then also need adjustment for consistency reasons.
Unlike the high bit of VEX.vvvv / EVEX.vvvv, EVEX.V' is not ignored
outside of 64-bit mode. Oddly enough there already are tests for these
cases, but their expectations were wrong. (This may have been based on
an old SDM version, where the restriction wasn't properly spelled out.)
With EVEX.W clear the instruction doesn't ignore the rounding mode, but
(like for other insns without rounding semantics) EVEX.b set causes #UD.
Hence the handling of EVEX.W needs to be done when processing
evex_rounding_64_mode, not at the decode stages.
Derive a new 64-bit testcase from the 32-bit one to cover the different
EVEX.W treatment in both cases.
netbsdpe was deprecated in c2ce831330e10dab4703094491f80b6b9a5c2289.
Since then, a release has passed (2.37), and it was marked obselete in
5c9cbf07f3f972ecffe13d858010b3179df17b32. Unless I am mistaken, that
means we can now remove support altogether.
All branches in the "active" code are remove, and the target is
additionally marked as obsolete next to the other removed ones for
libbfd and gdb.
Per [1] from the NetBSD toolchain list, PE/COFF support was removed a
decade ago. Furthermore, the sole mention of this target in the binutils
commit history was in 2002. Together, I'm led to believe this target
hasn't seen much attention in quite a while.
[1]: https://mail-index.netbsd.org/tech-toolchain/2021/06/16/msg003996.html
bfd/
* config.bfd: Remove netbsdpe entry.
binutils/
* configure.ac: Remove netbsdpe entry.
* testsuite/lib/binutils-common.exp (is_pecoff_format): Likewise.
* configure: Regenerate.
gas/
* configure.tgt: Remove netbsdpe entry.
gdb/
* configure.tgt: Add netbsdpe to removed targets.
ld/
* configure.tgt: Remove netbsdpe entry.
* testsuite/ld-bootstrap/bootstrap.exp: Likewise.
* Two add subset functions is redundant. Keep the riscv_add_implicit_subset,
and renamed it to riscv_add_subset. Besides, if the subset is added in order,
then we just add it at the tail of the subset list.
* Removed the "-march:" prefix from the error messages. Since not only the
-march= option will use the parser, but also the architecture elf attributes,
the default architecture setting and linker will use the same parser.
* Use a function, riscv_parse_check_conflicts, to check the conflicts
of extensions, including the rv64e and rv32q.
The rv32emc-elf/rv32i-elf/rv32gc-linux/rv64gc-elf/rv64gc-linux regressions
are tested and passed.
bfd/
* elfxx-riscv.c (riscv_lookup_subset): Check the subset tail list
first. If the subset is added in order, then we can just add it to
the tail without searching the whole list.
(riscv_add_subset): Replaced by riscv_add_implicit_subset.
(riscv_add_implicit_subset): Renamed to riscv_add_subset.
(riscv_parse_add_subset): Updated.
(riscv_parsing_subset_version): Removed the "-march:" prefix from
the error message.
(riscv_parse_prefixed_ext): Likewise.
(riscv_parse_std_ext): Likewise. And move the rv<xlen>e check
to riscv_parse_check_conflicts.
(riscv_parse_check_conflicts): New function used to check conflicts.
(riscv_parse_subset): Updated.
gas/
* testsuite/gas/riscv/march-fail-base-02.l: Updated.
* testsuite/gas/riscv/march-fail-unknown-std.l: Likewise.
gas/write.c provides a fallback TC_VALIDATE_FIX_SUB define that can be
a problem for some targets, the problem being that a non-zero
definition of TC_VALIDATE_FIX_SUB says that some uses of fx_subsy are
OK, in effect that the target will handle fx_subsy in md_apply_fix
and/or tc_gen_reloc. A lot of targets don't have the necessary
md_apply_fix and tc_gen_reloc support. So a safer default is to
disallow fx_subsy by default.
I've had a good look over target usage of fx_subsy, and think I've
caught all the cases where targets need TC_VALIDATE_FIX_SUB. Possible
failures would be limited to alpha, microblaze, ppc and s390 (the
targets that define UNDEFINED_DIFFERENCE_OK), or targets that generate
fixups with BFD_RELOC_GPREL32/16 and use a syntax explicitly showing
a difference expression.
* write.c (TC_VALIDATE_FIX_SUB): Default to 0.
* config/tc-hppa.h (TC_VALIDATE_FIX_SUB): Define.
* config/tc-microblaze.h (TC_VALIDATE_FIX_SUB): Define.
* config/tc-alpha.h (TC_VALIDATE_FIX_SUB): Define for ECOFF.
* config/tc-ppc.h (TC_VALIDATE_FIX_SUB): Don't define for ELF.
Do define for XCOFF.
DWARF sections have special names on AIX which need be handled
by objdump in order to correctly print them.
This patch also adds the correlation in bfd for future uses.
bfd/
* libxcoff.h (struct xcoff_dwsect_name): Add DWARF name.
* coff-rs6000.c (xcoff_dwsect_names): Update.
* coffcode.h (sec_to_styp_flags): Likewise.
(coff_new_section_hook): Likewise.
binutils/
* dwarf.h (struct dwarf_section): Add XCOFF name.
* dwarf.c (struct dwarf_section_display): Update.
* objdump.c (load_debug_section): Add XCOFF name handler.
(dump_dwarf_section): Likewise.
gas/
* config/tc-ppc.c (ppc_change_debug_section): Update to
match new name's field.
Since gcc commit, 3c70b3ca1ef58f302bf8c16d9e7c7bb8626408bf, we now enable
elf attributes for all riscv targets by default in gcc. Therefore, I
think binutils should have the same behavior, in case users are writing
assembly files. If --enable-default-riscv-attribute isn't set, then we
enable the elf attributes for all riscv targets by default.
ChangLog:
binutils/
* testsuite/binutils-all/readelf.s: Add comments for riscv.
* testsuite/binutils-all/readelf.s-64: Likewise.
* testsuite/binutils-all/readelf.s-64-unused: Likewise.
* testsuite/binutils-all/readelf.ss: Likewise.
* testsuite/binutils-all/readelf.ss-64: Likewise.
* testsuite/binutils-all/readelf.ss-64-unused: Likewise.
gas/
* configure.ac: If --enable-default-riscv-attribute isn't set,
then we enable the elf attributes for all riscv targets by
default.
* configure: Regenerated.
Some extern declarations differ in constnes to their definitions too.
Let's make sure this sort of thing doesn't happen again, but putting
the externs in a header where they belong.
gas/
* config/tc-nds32.c (nds32_keyword_gpr): Don't declare.
(md_begin): Constify k.
opcodes/
* nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
(nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
(nds32_field_table, nds32_opcode_table, nds32_keyword_table),
(nds32_opcodes, nds32_operand_fields, nds32_keywords),
(nds32_keyword_gpr): Move declarations to..
* nds32-asm.h: ..here, constifying to match definitions.
This is exporting the variable "opcodes" as a large writable blob.
This is not a namespace friendly name, so add a "microblaze" prefix,
and then sprinkle const over its definition & use.
Power10 prefixed instructions must not cross 64-byte boundaries.
This is already handled.
However, on XCOFF, the csect must be updated to match the new
alignment.
* config/tc-ppc.c (md_assemble): Update ppc_current_csect
alignment when finding prefixed instructions.
Commit 54758c3e398d made changes to the picojava support based on
https://sourceware.org/pipermail/binutils/2005-November/045136.html
An update from picojava to picojava II, I think. Unfortunately the
patch neglected any changes to the gas testsuite, resulting in
"FAIL: pj" since that date. This patch makes a few relatively simple
changes to cure the regression.
gas/
* config/tc-pj.c (md_apply_fix): Apply PJ_CODE_REL32 relocs.
* testsuite/gas/pj/ops.s: Update jsr, ret, getstatic,
putstatic, getfield, putfield, invokevirtual, invokespecial,
invokestatic, invokeinterface, goto_w, jsr_w assembly. Delete
version 1 picojava opcodes.
* testsuite/gas/pj/ops.d: Match expected output.
opcodes/
* pj-dis.c (print_insn_pj): Don't print trailing tab. Do
print separator for pcrel insns.
