3081 Commits

Author SHA1 Message Date
Jens Remus
f96fe7f454 s390: Optionally print instruction description in disassembly
Print instruction description as comment in disassembly with s390
architecture specific option "insndesc":

- For objdump it can be enabled with option "-M insndesc"
- In gdb it can be enabled with "set disassembler-options insndesc"

Since comments are not column aligned the output can enhanced for
readability by postprocessing using a filter such as "expand":

... | expand -t 8,16,24,32,40,80

Or when using in combination with objdump option --visualize-jumps:

... | expand | sed -e 's/ *#/\t#/' | expand -t 1,80

Note that the instruction descriptions add about 128 KB to s390-opc.o:

s390-opc.o without instruction descriptions: 216368 bytes
s390-opc.o with instruction descriptions   : 348432 bytes

binutils/
	* NEWS: Mention new s390-specific disassembler option
	  "insndesc".

include/
	* opcode/s390.h (struct s390_opcode): Add field to hold
	  instruction description.

opcodes/
	* s390-mkopc.c: Copy instruction description from s390-opc.txt
	  into generated operation code table s390-opc.tab.
	* s390-opc.c (s390_opformats): Provide NULL as description in
	  .insn pseudo-mnemonics opcode table.
	* s390-dis.c: Add s390-specific disassembler option "insndesc"
	  and optionally print the instruction description as comment in
	  the disassembly when it is specified.

gas/
	* testsuite/gas/s390/s390.exp: Add new test disassembly test
	  case "zarch-insndesc".
	* testsuite/gas/s390/zarch-insndesc.s: New test case for s390-
	  specific disassembler option "insndesc".
	* testsuite/gas/s390/zarch-insndesc.d: Likewise.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20 11:50:32 +01:00
Andrea Corallo
d645278cdf aarch64: Add FEAT_ITE support
This patch add support for FEAT_ITE "Instrumentation Extension" adding
the "trcit" instruction.

This is enabled by the +ite march flag.
2023-12-19 15:35:49 +01:00
Andrea Corallo
88b5a8ae13 aarch64: Add FEAT_SPECRES2 support
This patch add supports for FEAT_SPECRES2 "Enhanced speculation
restriction instructions" adding the "cosp" instruction.

This is mandatory v8.9-a/v9.4-a and optional v8.0-a+/v9.0-a+.  It is
enabled by the +predres2 march flag.
2023-12-19 15:35:49 +01:00
mengqinggang
dc5f359ed6 LoongArch: Add new relocation R_LARCH_CALL36
R_LARCH_CALL36 is used for medium code model function call pcaddu18i+jirl, and
these two instructions must adjacent.

The LoongArch ABI v2.20 at here: https://github.com/loongson/la-abi-specs.
2023-12-18 18:36:21 +08:00
Jin Ma
8cb16b6858 RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.
The description of instructions 'th.fmv.hw.x' and 'th.fmv.x.hw' of the
XTheadFmv extension in T-Head specific is incorrect, and it also has
some impact on the implementation of the binutils, so this patch
corrects this.

For details see:
https://github.com/T-head-Semi/thead-extension-spec/pull/34

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-fmv.d: Correct test.
	* testsuite/gas/riscv/x-thead-fmv.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_FMV_HW_X): Correct coding.
	(MASK_TH_FMV_HW_X): Likewise.
	(MATCH_TH_FMV_X_HW): Likewise.
	(MASK_TH_FMV_X_HW): Likewise.

opcodes/ChangeLog:

	* riscv-opc.c: Correct operands.
2023-12-14 09:54:19 +01:00
Tom Tromey
15c350f192 Add some new DW_IDX_* constants
I've reimplemented the .debug_names code in GDB -- it was quite far
from being correct, and the new implementation is much closer to what
is specified by DWARF.

However, the new writer in GDB needs to emit some symbol properties,
so that the reader can be fully functional.  This patch adds a few new
DW_IDX_* constants, and tries to document the existing extensions as
well.  (My patch series add more documentation of these to the GDB
manual as well.)

2023-12-10  Tom Tromey  <tom@tromey.com>

	* dwarf2.def (DW_IDX_GNU_internal, DW_IDX_GNU_external): Comment.
	(DW_IDX_GNU_main, DW_IDX_GNU_language, DW_IDX_GNU_linkage_name):
	New constants.
2023-12-10 14:55:22 -07:00
Andreas Schwab
1b183017aa Add basic support for RISC-V 64-bit EFI objects
This adds a new PEI target pei-riscv64-little.  Only objdump and objcopy
are supported.

bfd:
	* .gitignore: Add pe-riscv64igen.c.
	* Makefile.am (BFD64_BACKENDS): Add pei-riscv64.lo,
	pe-riscv64igen.lo.
	(BFD64_BACKENDS_CFILES): Add pei-riscv64.c.
	(BUILD_CFILES): Add pe-riscv64igen.c.
	(pe-riscv64igen.c): New rule.
	* Makefile.in: Regenerate.
	* bfd.c (bfd_get_sign_extend_vma): Add pei-riscv64-little.
	* coff-riscv64.c: New file.
	* coffcode.h (coff_set_arch_mach_hook, coff_set_flags)
	(coff_write_object_contents): Add riscv64 (riscv64_pei_vec)
	support.
	* config.bfd (targ_selvecs): Add riscv64_pei_vec to all riscv*
	targets.
	* configure.ac: Handle riscv64_pei_vec.
	* configure: Regenerate.
	* libpei.h (GET_OPTHDR_IMAGE_BASE, PUT_OPTHDR_IMAGE_BASE)
	(GET_OPTHDR_SIZE_OF_STACK_RESERVE)
	(PUT_OPTHDR_SIZE_OF_STACK_RESERVE)
	(GET_OPTHDR_SIZE_OF_STACK_COMMIT, PUT_OPTHDR_SIZE_OF_STACK_COMMIT)
	(GET_OPTHDR_SIZE_OF_HEAP_RESERVE, PUT_OPTHDR_SIZE_OF_HEAP_RESERVE)
	(GET_OPTHDR_SIZE_OF_HEAP_COMMIT, PUT_OPTHDR_SIZE_OF_HEAP_COMMIT)
	(GET_PDATA_ENTRY, _bfd_XX_bfd_copy_private_bfd_data_common)
	(_bfd_XX_bfd_copy_private_section_data)
	(_bfd_XX_get_symbol_info, _bfd_XX_only_swap_filehdr_out)
	(_bfd_XX_print_private_bfd_data_common)
	(_bfd_XXi_final_link_postscript, _bfd_XXi_only_swap_filehdr_out)
	(_bfd_XXi_swap_aouthdr_in, _bfd_XXi_swap_aouthdr_out)
	(_bfd_XXi_swap_aux_in, _bfd_XXi_swap_aux_out)
	(_bfd_XXi_swap_lineno_in, _bfd_XXi_swap_lineno_out)
	(_bfd_XXi_swap_scnhdr_out, _bfd_XXi_swap_sym_in)
	(_bfd_XXi_swap_sym_out, _bfd_XXi_swap_debugdir_in)
	(_bfd_XXi_swap_debugdir_out, _bfd_XXi_write_codeview_record)
	(_bfd_XXi_slurp_codeview_record) [COFF_WITH_peRiscV64]: Define.
	(_bfd_peRiscV64_print_ce_compressed_pdata): Declare.
	* peXXigen.c (_bfd_XXi_swap_aouthdr_in, _bfd_XXi_swap_aouthdr_out)
	(_bfd_XXi_swap_scnhdr_out, pe_print_pdata)
	(_bfd_XX_print_private_bfd_data_common)
	(_bfd_XX_bfd_copy_private_section_data)
	(_bfd_XXi_final_link_postscript): Support COFF_WITH_peRiscV64.
	* pei-riscv64.c: New file.
	* peicode.h (coff_swap_scnhdr_in, pe_ILF_build_a_bfd)
	(pe_ILF_object_p): Support COFF_WITH_peRiscV64.
	(jtab): Add dummy entry that traps.
	* targets.c (_bfd_target_vector): Add riscv64_pei_vec.

binutils:
	* testsuite/binutils-all/riscv/pei-riscv64.d: New.
	* testsuite/binutils-all/riscv/pei-riscv64.s: New.

include:
	* coff/riscv64.h: New file.
	* coff/pe.h (IMAGE_FILE_MACHINE_RISCV32)
	(IMAGE_FILE_MACHINE_RISCV64): Define.
2023-12-05 13:20:27 +01:00
Jens Remus
c5306fed7d s390: Support for jump visualization in disassembly
Add support for jump visualization for the s390 architecture in
disassembly:

objdump -d --visualize-jumps ...

Annotate the (conditional) jump and branch relative instructions with
information required for jump visualization:
- jump: Unconditional jump / branch relative.
- condjump: Conditional jump / branch relative.
- jumpsr: Jump / branch relative to subroutine.

Unconditional jump and branch relative instructions are annotated as
jump.
Conditional jump and branch relative instructions, jump / branch
relative on count/index, and compare and jump / branch relative
instructions are annotated as condjump.
Jump and save (jas, jasl) and branch relative and save (bras, brasl)
instructions are annotated as jumpsr (jump to subroutine).

Provide instruction information required for jump visualization during
disassembly.
The instruction type is provided after determining the opcode.
For non-code it is set to dis_noninsn. Otherwise it defaults to
dis_nonbranch. No annotation is done for data reference instructions
(i.e. instruction types dis_dref and dis_dref2). Note that the
instruction type needs to be provided before printing of the
instruction, as it is used in print_address_func() to translate the
argument value into an address if it is assumed to be a PC-relative
offset. Note that this is never the case on s390, as
print_address_func() is only called with addresses and never with
offsets.
The target of the (conditional) jump and branch relative instructions
is provided during print, when the PC relative operand is decoded.

include/
	* opcode/s390.h: Define opcode flags to annotate instruction
	  class information for jump visualization:
	  S390_INSTR_FLAG_CLASS_BRANCH, S390_INSTR_FLAG_CLASS_RELATIVE,
	  S390_INSTR_FLAG_CLASS_CONDITIONAL, and
	  S390_INSTR_FLAG_CLASS_SUBROUTINE.
	  Define opcode flags mask S390_INSTR_FLAG_CLASS_MASK for above
	  instruction class information.
	  Define helpers for common instruction class flag combinations:
	  S390_INSTR_FLAGS_CLASS_JUMP, S390_INSTR_FLAGS_CLASS_CONDJUMP,
	  and S390_INSTR_FLAGS_CLASS_JUMPSR.

opcodes/
	* s390-mkopc.c: Add opcode flags to annotate information
	  for jump visualization: jump, condjump, and jumpsr.
	* s390-opc.txt: Annotate (conditional) jump and branch relative
	  instructions with information for jump visualization.
	* s390-dis.c (print_insn_s390, s390_print_insn_with_opcode):
	  Provide instruction information for jump visualization.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-04 17:13:33 +00:00
Nelson Chu
248bf6de04 RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0
SiFive has define as set of flexible instruction for extending vector
coprocessor, it able to encoding opcode like .insn but with predefined
format.

List of instructions:
  sf.vc.x
  sf.vc.i
  sf.vc.vv
  sf.vc.xv
  sf.vc.iv
  sf.vc.fv
  sf.vc.vvv
  sf.vc.xvv
  sf.vc.ivv
  sf.vc.fvv
  sf.vc.vvw
  sf.vc.xvw
  sf.vc.ivw
  sf.vc.fvw
  sf.vc.v.x
  sf.vc.v.i
  sf.vc.v.vv
  sf.vc.v.xv
  sf.vc.v.iv
  sf.vc.v.fv
  sf.vc.v.vvv
  sf.vc.v.xvv
  sf.vc.v.ivv
  sf.vc.v.fvv
  sf.vc.v.vvw
  sf.vc.v.xvw
  sf.vc.v.ivw
  sf.vc.v.fvw

Spec of Xsfvcp
https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software

Co-authored-by: Hau Hsu <hau.hsu@sifive.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
2023-12-01 09:29:07 +08:00
Christoph Müllner
ea1bd00742 RISC-V: Zv*: Add support for Zvkb ISA extension
Back then when the support for the RISC-V vector crypto extensions
was merged, the specification was frozen, but not ratified.
A frozen specification is allowed to change within tight bounds
before ratification and this has happend with the vector crypto
extensions.

The following changes were applied:
* A new extension Zvkb was defined, which is a strict subset of Zvbb.
* Zvkn and Zvks include now Zvkb instead of Zvbb.

This patch implements these changes between the frozen and the
ratified specification.

Note, that this technically an incompatible change of Zvkn and Zvks,
but I am not aware of any project that depends on the currently
implemented behaviour of Zvkn and Zvks. So this patch should be fine.

Reported-By: Jerry Shih <jerry.shih@sifive.com>
Reported-By: Eric Biggers <ebiggers@kernel.org>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-12-01 01:48:27 +01:00
Jakub Jelinek
4a50820ee8 libiberty, ld: Use x86 HW optimized sha1
The following patch attempts to use x86 SHA ISA if available to speed
up in my testing about 2.5x sha1 build-id processing (in my case on
AMD Ryzen 5 3600) while producing the same result.
I believe AArch64 has similar HW acceleration for SHA1, perhaps it
could be added similarly.

Note, seems lld uses BLAKE3 rather than md5/sha1.  I think it would be
a bad idea to lie to users, if they choose --buildid=sha1, we should
be using SHA1, not some other checksum, but perhaps we could add some other
--buildid= styles and perhaps make one of the new the default.

Tested on x86_64-linux, both on Intel i9-7960X (which doesn't have
sha_ni ISA support) without/with the patch and on AMD Ryzen 5 3600
(which does have it) without/with the patch.

2023-11-28  Jakub Jelinek  <jakub@redhat.com>

include/
	* sha1.h (sha1_process_bytes_fn): New typedef.
	(sha1_choose_process_bytes): Declare.
libiberty/
	* configure.ac (HAVE_X86_SHA1_HW_SUPPORT): New check.
	* sha1.c: If HAVE_X86_SHA1_HW_SUPPORT is defined, include x86intrin.h
	and cpuid.h.
	(sha1_hw_process_bytes, sha1_hw_process_block,
	sha1_choose_process_bytes): New functions.
	* config.in: Regenerated.
	* configure: Regenerated.
ld/
	* ldbuildid.c (generate_build_id): Use sha1_choose_process_bytes ()
	instead of &sha1_process_bytes.
2023-11-28 13:29:58 +01:00
Jan Beulich
eb5e952f95 RISC-V: reduce redundancy in sign/zero extension macro insn handling
Fold M_{S,Z}EXTH, deriving signed-ness from the incoming mnemonic. Fold
riscv_ext()'s calls md_assemblef(), the first of which were entirely
identical, while the other pair differed in just a single character.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-11-24 09:53:55 +01:00
Jin Ma
d95ba7227e RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds permutation instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension
are documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	permutation instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VMVXS): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
2023-11-23 09:32:18 +08:00
Jin Ma
832cdeeccb RISC-V: Add vector mask instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds mask instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension
are documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	mask instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VMPOPCM): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
2023-11-23 09:32:12 +08:00
Jin Ma
1ba39b6fe5 RISC-V: Add floating-point arithmetic instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds floating-point arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	floating-point arithmetic instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VFSQRTV): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
2023-11-23 09:32:03 +08:00
Jin Ma
9a51da2636 RISC-V: Add fixed-point arithmetic instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds fixed-point arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	fixed-point arithmetic instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VAADDVV): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
2023-11-23 09:31:57 +08:00
Jin Ma
c63af675b9 RISC-V: Add integer arithmetic instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds integer arithmetic instructions for the
"XTheadVector" extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	integer arithmetic instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VADCVVM): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
2023-11-23 09:31:52 +08:00
Jin Ma
4d8f1ff3bc RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds the sub-extension "XTheadZvamo" for the
"XTheadVector" extension, and it provides AMO instructions
for T-Head VECTOR vendor extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Add support
	for "XTheadZvamo" extension.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* doc/c-riscv.texi:
	* testsuite/gas/riscv/x-thead-vector-zvamo.d: New test.
	* testsuite/gas/riscv/x-thead-vector-zvamo.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VAMOADDWV): New.
	* opcode/riscv.h (enum riscv_insn_class): Add insn class.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
2023-11-23 09:31:48 +08:00
Jin Ma
763c4daa35 RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore it
makes sense to group them into smaller chunks in form of vendor
extensions.

This patch adds provides load/store segment instructions for T-Head VECTOR
vendor extension, which same as the "Zvlsseg" extension in RVI 0.71 vector
extension, but belongs to the "XTheadVector" extension. The 'th' prefix
and the "XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add test.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VLSEG2BV): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
2023-11-23 09:31:43 +08:00
Jin Ma
0bd0e6522a RISC-V: Add load/store instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds load/store instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension are
documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	load/store instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VLBV): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
2023-11-23 09:31:38 +08:00
Jin Ma
6fdd02bb1f RISC-V: Add CSRs for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions.
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the CSRs for XTheadVector. Because of the
conflict between encoding and teh 'V' extension, it is implemented
by alias. The 'th' prefix and the "XTheadVector" extension are
documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* config/tc-riscv.c (enum riscv_csr_class): Add the class for
	the CSRs of the "XTheadVector" extension.
	(riscv_csr_address): Likewise.
	* testsuite/gas/riscv/x-thead-vector-csr-warn.d: New test.
	* testsuite/gas/riscv/x-thead-vector-csr-warn.l: New test.
	* testsuite/gas/riscv/x-thead-vector-csr.d: New test.
	* testsuite/gas/riscv/x-thead-vector-csr.s: New test.

include/ChangeLog:

	* opcode/riscv-opc.h (DECLARE_CSR_ALIAS): Likewise.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Prefix the CSRs disassembly with 'th'.
2023-11-23 09:31:29 +08:00
Jin Ma
86fbfedd71 RISC-V: Add T-Head VECTOR vendor extension.
T-Head has a range of vendor-specific instructions ([2]).
Therefore it makes sense to group them into smaller chunks
in form of vendor extensions.

This patch adds the "XTheadVector" extension, a collection of
T-Head-specific vector instructions. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the RISC-V
toolchain conventions ([1]).

Here are some things that need to be explained:
The "XTheadVector" extension is not a custom-extension, but
a non-standard non-conforming extension. The encoding space
of the "TheadVector" instructions overlaps with those of
the 'V' extension. This encoding space conflict is not on
purpose, but the result of issues in the past that have
been resolved since. Therefore, the "XTheadVector" extension
and the 'V' extension are in conflict.

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
[2] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_parse_check_conflicts): The
	"XTheadVector" extension and the 'V' extension are in conflict.
	(riscv_multi_subset_supports): Likewise..
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* doc/c-riscv.texi:
	* testsuite/gas/riscv/x-thead-vector-fail.d: New test.
	* testsuite/gas/riscv/x-thead-vector-fail.l: New test.
	* testsuite/gas/riscv/x-thead-vector.s: New test.

include/ChangeLog:

	* opcode/riscv.h (enum riscv_insn_class):
2023-11-23 09:31:25 +08:00
Srinath Parvathaneni
44167ca8da aarch64: Add support for VMSA feature enhancements.
This patch adds the permission model enhancement and memory
attribute index enhancement features and their corresponding
system registers in AArch64 assembler.
Permission Indirection Extension (FEAT_S1PIE, FEAT_S2PIE)
Permission Overlay Extension (FEAT_S1POE, FEAT_S2POE)
Memory Attribute Index Enhancement (FEAT_AIE)
Extension to Translation Control Registers (FEAT_TCR2)

These features are available by default from Armv9.4-A architecture.
2023-11-16 14:29:30 +00:00
Srinath Parvathaneni
281fda33bc aarch64: Add new AT system instructions.
This patch adds 3 new AT system instructions through FEAT_ATS1A
feature, which are available by default from Armv9.4-A architecture.
2023-11-16 14:24:30 +00:00
Srinath Parvathaneni
311276f10c aarch64: Add support to new features in RAS extension.
This patch also adds support for:
1. FEAT_RASv2 feature and "ERXGSR_EL1" system register.
RASv2 feature is enabled by passing +rasv2 to -march
(eg: -march=armv8-a+rasv2).

2. FEAT_SCTLR2 and following system registers.
SCTLR2_EL1, SCTLR2_EL12, SCTLR2_EL2 and SCTLR2_EL3.

3. FEAT_FGT2 and following system registers.
HDFGRTR2_EL2, HDFGWTR2_EL2, HFGRTR2_EL2, HFGWTR2_EL2

4. FEAT_PFAR and following system registers.
PFAR_EL1, PFAR_EL2 and PFAR_EL12.

FEAT_RASv2, FEAT_SCTLR2, FEAT_FGT2 and FEAT_PFAR features are by default
enabled from Armv9.4-A architecture.

This patch also adds support for two read only system registers
id_aa64mmfr3_el1 and id_aa64mmfr4_el1, which are available from
Armv8-A Architecture.
2023-11-16 12:18:34 +00:00
Srinath Parvathaneni
43e228e98c aarch64: Add features to the Statistical Profiling Extension.
This patch adds features to the Statistical Profiling Extension,
identified as FEAT_SPEv1p4, FEAT_SPE_FDS, and FEAT_SPE_CRR, which
are enabled by default from Armv9.4-A.

Also adds support for system register "pmsdsfr_el1".
2023-11-16 12:16:56 +00:00
Simon Marchi
a7a0cb6c92 bfd, binutils: add gfx11 amdgpu architectures
Teach bfd and readelf about some recent gfx11 architectures.  This code
is taken from the rocgdb 5.7.x branch [1].

[1] https://github.com/rocm-Developer-Tools/rocgdb/tree/rocm-5.7.x

bfd/ChangeLog:

	* archures.c (bfd_mach_amdgcn_gfx1100, bfd_mach_amdgcn_gfx1101,
	bfd_mach_amdgcn_gfx1102): New.
	* bfd-in2.h (bfd_mach_amdgcn_gfx1100, bfd_mach_amdgcn_gfx1101,
	bfd_mach_amdgcn_gfx1102): New.
	* cpu-amdgcn.c (arch_info_struct): Add entries for
	bfd_mach_amdgcn_gfx1100, bfd_mach_amdgcn_gfx1101,
	bfd_mach_amdgcn_gfx1102.

binutils/ChangeLog:

	* readelf.c (decode_AMDGPU_machine_flags): Handle gfx1100,
	gfx1101, gfx1102.

include/ChangeLog:

	* elf/amdgpu.h (EF_AMDGPU_MACH_AMDGCN_GFX1100,
	EF_AMDGPU_MACH_AMDGCN_GFX1101,
	EF_AMDGPU_MACH_AMDGCN_GFX1102): New.

Change-Id: I95a8a62942e359781a1c9fa2079950fbcf2a78b8
Co-Authored-By: Laurent Morichetti <laurent.morichetti@amd.com>
Cc: Lancelot Six <lancelot.six@amd.com>
2023-11-10 13:20:22 -05:00
Ying Huang
d173146d9b MIPS: Change all E_MIPS_* to EF_MIPS_* 2023-11-10 14:03:17 +00:00
Nick Clifton
e922d1eaa3 Add ability to change linker warning messages into errors when reporting executable stacks and/or executable segments.
include
  * bfdlink.h (struct bfd_link_info): Update descriptions of the 'execstack', 'noexecstack' and 'warn_execstack' fields. Add 'error_exectack' and 'warn_is_error_for_rwx_segments' fields.

  bfd
  * elf.c (assign_file_positions_except_relocs): Turn warnings about executable segments into errors if so requested.
  * elflink.c (bfd_elf_size_dynamic_sections): Turn warnings about executable stacks into errors if so requested.

  ld
  * ldlex.h (enum option_values): Add OPTION_ERROR_EXECSTACK, OPTION_NO_ERROR_EXECSTACK, OPTION_WARN_EXECSTACK_OBJECTS, OPTION_ERROR_RWX_SEGMENTS and OPTION_NO_ERROR_RWX_SEGMENTS. (struct ld_option): Add new long options. (parse_args): Parse new long options. (elf_static_list_options): Display the new options.
  * ld.texi: Document the new command line options.
  * configure.ac (error-execstack): New configuration option. (error-rwx-segments): New configuration option.
  * emultempl/elf.em (_before_parse): Initialse the new linkinfo fields.
  * NEWS: Mention the new features.
  * config.in: Regenerate.
  * configure: Regenerate.
  * testsuite/ld-elf/commonpage2.d: Disable errors for RWX segments and/or executable stacks.
  * testsuite/ld-elf/elf.exp: Likewise.
  * testsuite/ld-elf/header.d: Likewise.
  * testsuite/ld-elf/loadaddr1.d: Likewise.
  * testsuite/ld-elf/loadaddr2.d: Likewise.
  * testsuite/ld-elf/maxpage4.d: Likewise.
  * testsuite/ld-elf/nobits-1.d: Likewise.
  * testsuite/ld-elf/note-1.d: Likewise.
  * testsuite/ld-elf/orphan-10.d: Likewise.
  * testsuite/ld-elf/orphan-11.d: Likewise.
  * testsuite/ld-elf/orphan-12.d: Likewise.
  * testsuite/ld-elf/orphan-5.d: Likewise.
  * testsuite/ld-elf/orphan-7.d: Likewise.
  * testsuite/ld-elf/orphan-8.d: Likewise.
  * testsuite/ld-elf/orphan-9.d: Likewise.
  * testsuite/ld-elf/orphan-region.d: Likewise.
  * testsuite/ld-elf/orphan.d: Likewise.
  * testsuite/ld-elf/pr19539.d: Likewise.
  * testsuite/ld-elf/pr26256-1a.d: Likewise.
  * testsuite/ld-elf/pr26907.d: Likewise.
  * testsuite/ld-elf/pr28597.d: Likewise.
  * testsuite/ld-elf/retain2.d: Likewise.
  * testsuite/ld-elf/shared.exp: Likewise.
  * testsuite/ld-elf/size-1.d: Likewise.
  * testsuite/ld-elf/textaddr7.d: Likewise.
  * testsuite/ld-elf/warn1.d: Likewise.
  * testsuite/ld-elf/warn2.d: Likewise.
  * testsuite/ld-i386/discarded1.d: Likewise.
  * testsuite/ld-i386/pr19175.d: Likewise.
  * testsuite/ld-i386/pr19539.d: Likewise.
  * testsuite/ld-i386/pr23189.d: Likewise.
  * testsuite/ld-plugin/lto-3r.d: Likewise.
  * testsuite/ld-plugin/lto-5r.d: Likewise.
  * testsuite/ld-plugin/lto.exp: Likewise.
  * testsuite/ld-powerpc/ppc476-shared.d: Likewise.
  * testsuite/ld-powerpc/ppc476-shared2.d: Likewise.
  * testsuite/ld-powerpc/pr28827-2.d: Likewise.
  * testsuite/ld-s390/s390.exp: Likewise.
  * testsuite/ld-scripts/align2a.d: Likewise.
  * testsuite/ld-scripts/align2b.d: Likewise.
  * testsuite/ld-scripts/align5.d: Likewise.
  * testsuite/ld-scripts/alignof.exp: Likewise.
  * testsuite/ld-scripts/crossref.exp: Likewise.
  * testsuite/ld-scripts/defined2.d: Likewise.
  * testsuite/ld-scripts/defined3.d: Likewise.
  * testsuite/ld-scripts/defined5.d: Likewise.
  * testsuite/ld-scripts/pr14962.d: Likewise.
  * testsuite/ld-scripts/pr18963.d: Likewise.
  * testsuite/ld-scripts/pr20302.d: Likewise.
  * testsuite/ld-scripts/print-memory-usage.exp: Likewise.
  * testsuite/ld-scripts/rgn-at1.d: Likewise.
  * testsuite/ld-scripts/rgn-at10.d: Likewise.
  * testsuite/ld-scripts/rgn-at4.d: Likewise.
  * testsuite/ld-scripts/rgn-at6.d: Likewise.
  * testsuite/ld-scripts/rgn-at8.d: Likewise.
  * testsuite/ld-scripts/rgn-at9.d: Likewise.
  * testsuite/ld-scripts/rgn-over1.d: Likewise.
  * testsuite/ld-scripts/rgn-over2.d: Likewise.
  * testsuite/ld-scripts/rgn-over4.d: Likewise.
  * testsuite/ld-scripts/rgn-over5.d: Likewise.
  * testsuite/ld-scripts/rgn-over6.d: Likewise.
  * testsuite/ld-scripts/script.exp: Likewise.
  * testsuite/ld-scripts/sizeof.exp: Likewise.
  * testsuite/ld-scripts/sort-file.d: Likewise.
  * testsuite/ld-x86-64/discarded1.d: Likewise.
  * testsuite/ld-x86-64/pr19175.d: Likewise.
  * testsuite/ld-x86-64/pr19539a.d: Likewise.
  * testsuite/ld-x86-64/pr19539b.d: Likewise.
  * testsuite/ld-x86-64/pr23189.d: Likewise.
2023-11-10 11:37:27 +00:00
Lulu Cai
98712e137e Add support for ilp32 register alias. 2023-11-10 14:45:09 +08:00
Victor Do Nascimento
f0d70d8ee6 aarch64: Add arch support for LSE128 extension
Enable the `+lse128' feature modifier which, together with new
internal feature flags, enables LSE128 instructions, which are
represented via the new `_LSE128_INSN' macro.

gas/ChangeLog:

	* config/tc-aarch64.c (aarch64_features): Add new "lse128"
	entry.

include/ChangeLog:

	* include/opcode/aarch64.h (enum aarch64_feature_bit): New
	AARCH64_FEATURE_LSE128 feature bit.
	(enum aarch64_insn_class): New lse128_atomic instruction class.

opcodes/ChangeLog:

	* opcodes/aarch64-tbl.h (aarch64_feature_lse128): New.
	(LSE128): Likewise.
	(_LSE128_INSN): Likewise.
2023-11-07 21:54:19 +00:00
Victor Do Nascimento
6219f9dae7 aarch64: Add LSE128 instruction operand support
Given the particular encoding of the LSE128 instructions, create the
necessary shared input+output operand register description and
handling in the code to allow for the encoding of the LSE128 128-bit
atomic operations.

gas/ChangeLog:

	* config/tc-aarch64.c (parse_operands):

include/ChangeLog:

	* opcode/aarch64.h (enum aarch64_opnd):

opcodes/ChangeLog:

	* aarch64-opc.c (fields):
	(aarch64_print_operand):
	* aarch64-opc.h (enum aarch64_field_kind):
	* aarch64-tbl.h (AARCH64_OPERANDS):
2023-11-07 21:53:59 +00:00
Victor Do Nascimento
9203a155ee aarch64: Add THE system register support
Add Binutils support for system registers associated with the
Translation Hardening Extension (THE).

In doing so, we also add core feature support for THE, enabling its
associated feature flag and implementing the necessary
feature-checking machinery.

Regression tested on aarch64-linux-gnu, no regressions.

gas/ChangeLog:

	* config/tc-aarch64.c (aarch64_features): Add "+the" feature modifier.
	* doc/c-aarch64.texi (AArch64 Extensions): Update
	documentation for `the' option.
	* testsuite/gas/aarch64/sysreg-8.s: Add tests for `the'
	associated system registers.
	* testsuite/gas/aarch64/sysreg-8.d: Likewise.

include/ChangeLog:

	* opcode/aarch64.h (enum aarch64_feature_bit): Add
	AARCH64_FEATURE_THE.

opcode/ChangeLog:

	* aarch64-opc.c (aarch64_sys_ins_reg_supported_p): Add `the'
	system register check support.
	* aarch64-sys-regs.def: Add `rcwmask_el1' and `rcwsmask_el1'
	* aarch64-tbl.h: Define `THE' preprocessor macro.
2023-11-07 20:38:11 +00:00
Mary Bennett
d1bd9787f9 RISC-V: Add support for XCValu extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvalu`
          instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Added the necessary
          operands for the extension.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Noted XCValu as an additional ISA extension
          for CORE-V.
	* testsuite/gas/riscv/cv-alu-boundaries.d: New test.
	* testsuite/gas/riscv/cv-alu-boundaries.l: New test.
	* testsuite/gas/riscv/cv-alu-boundaries.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-march.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-march.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-march.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-01.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-01.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-01.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-02.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-02.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-02.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-03.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-03.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-03.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-04.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-04.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-04.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-05.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-05.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-05.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-06.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-06.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-06.s: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-07.d: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-07.l: New test.
	* testsuite/gas/riscv/cv-alu-fail-operand-07.s: New test.
	* testsuite/gas/riscv/cv-alu-insns.d: New test.
	* testsuite/gas/riscv/cv-alu-insns.s: New test.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Disassemble xcb operand.
	* riscv-opc.c: Defined the MASK and added XCValu instructions.

include/ChangeLog:

	* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
          for XCValu.
	* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
          for XCValu.
	(enum riscv_insn_class): Added the XCValu instruction class.
2023-11-07 12:06:32 +08:00
Mary Bennett
ccb388ca39 RISC-V: Add support for XCVmac extension in CV32E40P
Spec: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html

Contributors:
  Mary Bennett <mary.bennett@embecosm.com>
  Nandni Jamnadas <nandni.jamnadas@embecosm.com>
  Pietra Ferreira <pietra.ferreira@embecosm.com>
  Charlie Keaney
  Jessica Mills
  Craig Blackmore <craig.blackmore@embecosm.com>
  Simon Cook <simon.cook@embecosm.com>
  Jeremy Bennett <jeremy.bennett@embecosm.com>
  Helene Chelin <helene.chelin@embecosm.com>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_multi_subset_supports): Added `xcvmac`
          instruction class.
	(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

	* config/tc-riscv.c (validate_riscv_insn): Added the necessary
          operands for the extension.
	(riscv_ip): Likewise.
	* doc/c-riscv.texi: Noted XCVmac as an additional ISA extension
          for CORE-V.
	* testsuite/gas/riscv/cv-mac-fail-march.d: New test.
	* testsuite/gas/riscv/cv-mac-fail-march.l: New test.
	* testsuite/gas/riscv/cv-mac-fail-march.s: New test.
	* testsuite/gas/riscv/cv-mac-fail-operand.d: New test.
	* testsuite/gas/riscv/cv-mac-fail-operand.l: New test.
	* testsuite/gas/riscv/cv-mac-fail-operand.s: New test.
	* testsuite/gas/riscv/cv-mac-insns.d: New test.
	* testsuite/gas/riscv/cv-mac-insns.s: New test.

opcodes/ChangeLog:

	* riscv-dis.c (print_insn_args): Disassemble information with
          the EXTRACT macro implemented.
	* riscv-opc.c: Defined the MASK and added
          XCVmac instructions.

include/ChangeLog:

	* opcode/riscv-opc.h: Added corresponding MATCH and MASK macros
          for XCVmac.
	* opcode/riscv.h: Added corresponding EXTRACT and ENCODE macros
          for uimm.
	(enum riscv_insn_class): Added the XCVmac instruction class.
2023-11-07 12:06:27 +08:00
Nelson Chu
0c4b8ed69c RISC-V: Moved out linker internal relocations after R_RISCV_max.
Just the lightest modifications about this, without any further checks and
considering --emit-relocs.  We will need to improve it in the future, but
first do this to avoid conflicts between linker internal relocations and the
new definition of psabi.  For example, TLSDESC relocs.

Passed riscv-gnu-toolchain regressions, so should be safe enough to commit.

Co-authored-by: Tsukasa OI <research_trasio@irq.a4lg.com>

bfd/
	* reloc.c: Removed linker internal relocations.
	* bfd-in2.h: Regenerated.
	* libbfd.h: Regenerated.
	* elfnn-riscv.c: Defined R_RISCV_DELETE in include/elf/riscv.h.
	* elfxx-riscv.c (howto_table, howto_table_internal): Moved linker
	internal relocations from howto_table into howto_table_internal.
	(riscv_reloc_map): Removed linker internal relocations mapping.
	(riscv_elf_rtype_to_howto): Return howto of linker internal
	relocations from howto_table_internal.
include/
	* elf/riscv.h: Defined linker internal relocations after R_RISCV_max.
2023-11-06 17:21:42 +08:00
Jan Beulich
c76820a017 RISC-V: reduce redundancy in load/store macro insn handling
Within the groups L{B,BU,H,HU,W,WU,D}, S{B,H,W,D}, FL{H,W,D,Q}, and
FS{H,W,D,Q} the sole difference between the handling is the insn
mnemonic passed to the common handling functions. The intended mnemonic,
however, can easily be retrieved. Furthermore leverags that Sx and FSx
are then handled identically, too, and hence their cases can also be
folded.
2023-11-03 10:03:36 +01:00
Srinath Parvathaneni
c58f84d899 aarch64: Add support for GCSB DSYNC instruction.
This patch adds support for Guarded control stack data synchronization
instruction (GCSB DSYNC). This instruction is allocated to existing
HINT space and uses the HINT number 19 and to match this an entry is
added to the aarch64_hint_options array.
2023-11-02 13:09:26 +00:00
srinath
f985c2512a aarch64: Add support for GCS extension.
This patch adds for Guarded Control Stack Extension (GCS) extension. GCS feature is
optional from Armv9.4-A architecture and enabled by passing +gcs option to -march
(eg: -march=armv9.4-a+gcs) or using ".arch_extension gcs" directive in the assembly file.

Also this patch adds support for GCS instructions gcspushx, gcspopcx, gcspopx,
gcsss1, gcsss2, gcspushm, gcspopm, gcsstr and gcssttr.
2023-11-02 13:06:00 +00:00
Srinath Parvathaneni
6c0ecdbad7 aarch64: Add support for Check Feature Status Extension.
This patch adds support for Check Feature Status Extension (CHK) which
is mandatory from Armv8.0-A. Also this patch supports "chkfeat" instruction
(hint #40).
2023-11-02 12:45:08 +00:00
srinath
8cee11cacc aarch64: Add support for Armv8.9-A and Armv9.4-A Architectures.
This patch adds AArch64 support for Armv8.9-A architecture (-march=armv8.9-a)
and Armv9.4-A architecture (-march=armv9.4-a).
2023-11-02 12:43:03 +00:00
Nick Clifton
a4a51292bb Accept and ignore the R_BPF_64_NODLYD32 relocation. 2023-10-30 12:18:45 +00:00
Neal Frager
d605374748 bfd: microblaze: Add 32_NONE reloc type
This patch adds the R_MICROBLAZE_32_NONE relocation type.
This is a 32-bit reloc that stores the 32-bit pc relative
value in two words (with an imm instruction).

Add test case to gas test suite.

Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-20 07:12:30 -07:00
Tsukasa OI
6f85247eec RISC-V: Remove semicolons from DECLARE_INSN
This is for consistency and to prevent possible unnecessary errors due
to this inconsistency.

include/ChangeLog:

	* opcode/riscv-opc.h (DECLARE_INSN): Remove semicolons from the
	end of each entry.
2023-10-19 01:06:34 +00:00
Tsukasa OI
f46ff02f18 RISC-V: Fix typo
include/ChangeLog:

	* opcode/riscv-opc.h: Fix typo.
2023-10-17 02:09:44 +00:00
mengqinggang
1fb3cdd87e LoongArch/GAS: Add support for branch relaxation
For the instructions of R_LARCH_B16/B21, if the immediate overflow,
add a B instruction and R_LARCH_B26 relocation.

For example:

.L1
  ...
  blt $t0, $t1, .L1
    R_LARCH_B16

change to:

.L1
  ...
  bge $t0, $t1, .L2
  b .L1
    R_LARCH_B26
.L2
2023-10-10 16:34:33 +08:00
cailulu
816029e067 as: add option for generate R_LARCH_32/64_PCREL.
Some older kernels cannot handle the newly generated R_LARCH_32/64_PCREL,
so the assembler generates R_LARCH_ADD32/64+R_LARCH_SUB32/64 by default,
and use the assembler option mthin-add-sub to generate R_LARCH_32/64_PCREL
as much as possible.

The Option of mthin-add-sub does not affect the generation of R_LARCH_32_PCREL
relocation in .eh_frame.
2023-10-08 09:18:12 +08:00
Michael J. Eager
a3f6124483 Revert "opcodes: microblaze: Add new bit-field instructions"
This reverts commit 6bbf249557ba17cfebe01c67370df4da9e6a56f9.

Maciej W. Rozycki <macro@orcam.me.uk>:
 Yet it has caused numerous regressions:

microblaze-elf  +FAIL: unordered .debug_info references to .debug_ranges
microblaze-elf  +FAIL: binutils-all/pr26548
microblaze-elf  +FAIL: readelf -Wwi pr26548e (reason: unexpected output)
microblaze-elf  +FAIL: readelf --debug-dump=loc locview-1 (reason: unexpected output) Yet it has caused numerous regressions:
microblaze-elf  +FAIL: unordered .debug_info references to .debug_ranges
microblaze-elf  +FAIL: binutils-all/pr26548
microblaze-elf  +FAIL: readelf -Wwi pr26548e (reason: unexpected output)
...
2023-10-07 15:33:10 -07:00
Ilya Leoshkevich
7a3bb62d82 gdb: support rseq auxvs
Linux kernel commit commit 317c8194e6ae ("rseq: Introduce feature size
and alignment ELF auxiliary vector entries") introduced two new auxvs:
AT_RSEQ_FEATURE_SIZE and AT_RSEQ_ALIGN.  Support them in GDB.  This
fixes auxv.exp on kernels >= v6.3.

Change-Id: I8966c4d5c73eb7b45de6d410a9b28a6628edad2e
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=30540
Approved-By: Tom Tromey <tom@tromey.com>
2023-10-06 21:29:11 -04:00
Neal Frager
6bbf249557 opcodes: microblaze: Add new bit-field instructions
This patches adds new bsefi and bsifi instructions.
BSEFI- The instruction shall extract a bit field from a
register and place it right-adjusted in the destination register.
The other bits in the destination register shall be set to zero.
BSIFI- The instruction shall insert a right-adjusted bit field
from a register at another position in the destination register.
The rest of the bits in the destination register shall be unchanged.

Further documentation of these instructions can be found here:
https://docs.xilinx.com/v/u/en-US/ug984-vivado-microblaze-ref

This patch has been tested for years of AMD Xilinx Yocto
releases as part of the following patch set:

https://github.com/Xilinx/meta-xilinx/tree/master/meta-microblaze/recipes-devtools/binutils/binutils

Signed-off-by: nagaraju <nagaraju.mekala@amd.com>
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@amd.com>
Signed-off-by: Neal Frager <neal.frager@amd.com>
Signed-off-by: Michael J. Eager <eager@eagercon.com>
2023-10-06 10:53:45 -07:00