4648 Commits

Author SHA1 Message Date
Alan Modra
3838f0bc10 LoongArch: Commas inside double quotes
This adds an extra feature: Commas inside double quotes are not an
arg delimiter, and thus can be part of the arg.

	* loongarch-coder.c (loongarch_split_args_by_comma): Commas
	inside quotes are not arg delimiters.
2023-12-30 12:59:23 +10:30
changjiachen
b449f8428b LoongArch: opcodes: Add support for tls le relax.
Add new opcode for tls le relax.

	opcode/ChangeLog:

	* loongarch-opc.c: Add new loongarch opcode.
2023-12-29 15:11:00 +08:00
Jin Ma
77d242a06e RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extension
In order to make it easier to complete the compiler's support for
the XTheadVector extension and to be as compatible as possible
with the programming model of the 'V' extension ([1]), we consider
adding a few pseudo instructions ([2]).

th.vmmv.m vd,vs		=> th.vmand.mm vd,vs,vs
th.vneg.v vd,vs		=> th.vrsub.vx vd,vs,x0
th.vncvt.x.x.v vd,vs,vm	=> th.vnsrl.vx vd,vs,x0,vm
th.vfneg.v vd,vs	=> th.vfsgnjn.vv vd,vs,vs
th.vfabs.v vd,vs	=> th.vfsgnjx.vv vd,vs,vs

Ref:
[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641302.html
[2] https://github.com/T-head-Semi/thead-extension-spec/pull/40

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for new
	pseudoinstructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

opcodes/ChangeLog:

	* riscv-opc.c: Add new pseudoinstructions.
2023-12-29 08:55:30 +08:00
Hu, Lin1
cca90632f8 Support APX JMPABS for disassembler
gas/ChangeLog:

	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/x86-64-apx-jmpabs-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-apx-jmpabs-inval.d: Ditto.
	* testsuite/gas/i386/x86-64-apx-jmpabs-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-apx-jmpabs.d: Ditto.
	* testsuite/gas/i386/x86-64-apx-jmpabs.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (JMPABS_Fixup): New Fixup function to disassemble jmpabs.
	(print_insn): Add #UD exception for jmpabs.
	(dis386): Modify a1 unit for support jmpabs.
	* i386-mnem.h: Regenerated.
	* i386-opc.tbl: New insns.
	* i386-tbl.h: Regenerated.
2023-12-28 11:52:52 +00:00
Cui, Lili
ac32c879b2 Support APX pushp/popp
gas/ChangeLog:

	* config/tc-i386.c (process_operands): Handle "PUSHP/POPP requires
	rex2.w == 1."
	* testsuite/gas/i386/x86-64.exp: Add new test for PUSHP/POPP.
	* testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d: New test.
	* testsuite/gas/i386/x86-64-apx-pushp-popp-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-apx-pushp-popp-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-apx-pushp-popp.d: Ditto.
	* testsuite/gas/i386/x86-64-apx-pushp-popp.s: Ditto.

opcodes/ChangeLog:

	* i386-dis.c (putop): print pushp and popp.
	* i386-opc.tbl: Added new insns.
	* i386-init.h : Regenerated.
	* i386-mnem.h : Regenerated.
	* i386-tbl.h: Regenerated.
2023-12-28 11:45:14 +00:00
Mo, Zewei
08a98d4c13 Support APX Push2/Pop2
PPX functionality for PUSH/POP is not implemented in this patch
and will be implemented separately.

gas/ChangeLog:

2023-12-28  Zewei Mo <zewei.mo@intel.com>
            H.J. Lu  <hongjiu.lu@intel.com>
            Lili Cui <lili.cui@intel.com>

	* config/tc-i386.c: (enum i386_error):
	New unsupported_rsp_register and invalid_src_register_set.
	(md_assemble): Add handler for unsupported_rsp_register and
	invalid_src_register_set.
	(check_APX_operands): Add invalid check for push2/pop2.
	(match_template): Handle check_APX_operands.
	* testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/x86-64-apx-push2pop2.d: New test.
	* testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto.
	* testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto.
	* testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto.
	* testsuite/gas/i386/apx-push2pop2-inval.s: Ditto.
	* testsuite/gas/i386/apx-push2pop2-inval.d: Ditto.
	* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added bad
	testcases for POP2.
	* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto.

opcodes/ChangeLog:

	* i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F.
	* i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_R_0 and EVEX_W_MAP4_FF_R_6
	* i386-dis-evex.h: Add REG_EVEX_MAP4_8F.
	* i386-dis.c (PUSH2_POP2_Fixup): Add special handling for PUSH2/POP2.
	(get_valid_dis386): Add handler for vector length and address_mode for
	APX-Push2/Pop2 insn.
	(nd): define nd as b for EVEX-promoted instrutions.
	(OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn.
	* i386-gen.c: Add Push2Pop2 bitfield.
	* i386-opc.h: Regenerated.
	* i386-opc.tbl: Regenerated.
2023-12-28 11:41:45 +00:00
konglin1
3083f37643 Support APX NDD
opcodes/ChangeLog:

	* opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80,
	REG_EVEX_MAP4_81, REG_EVEX_MAP4_83,  REG_EVEX_MAP4_F6,
	REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF.
	* opcodes/i386-dis-evex.h: Add NDD insn.
	* opcodes/i386-dis.c (nd): New define.
	(VexGb): Ditto.
	(VexGv): Ditto.
	(get_valid_dis386): Change for NDD decode.
	(print_insn): Ditto.
	(putop): Ditto.
	(intel_operand_size): Ditto.
	(OP_E_memory): Ditto.
	(OP_VEX): Ditto.
	* opcodes/i386-opc.h (VexVVVV_DST): New.
	* opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV.
	* opcodes/i386-tbl.h: Regenerated.

gas/ChangeLog:

	* gas/config/tc-i386.c (operand_size_match):
	Support APX NDD that the number of operands is 3.
	(build_apx_evex_prefix): Change for ndd encode.
	(process_operands): Ditto.
	(build_modrm_byte): Ditto.
	(match_template): Support swap the first two operands for
	APX NDD.
	* testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd.
	* testsuite/gas/i386/x86-64-apx-ndd.d: New test.
	* testsuite/gas/i386/x86-64-apx-ndd.s: Ditto.
	* testsuite/gas/i386/x86-64-pseudos.d: Add test.
	* testsuite/gas/i386/x86-64-pseudos.s: Ditto.
	* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto.
	* testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
2023-12-28 11:37:16 +00:00
Cui, Lili
6177c84d5e Support APX GPR32 with extend evex prefix
This patch adds non-ND, non-NF forms of EVEX promotion insn.

EVEX extension of legacy instructions:
  All promoted legacy instructions are placed in EVEX map 4, which is
  currently reserved.
EVEX extension of EVEX instructions:
  All existing EVEX instructions are extended by APX using the extended
  EVEX prefix, so that they can access all 32 GPRs.
EVEX extension of VEX instructions:
  Promoting a VEX instruction into the EVEX space does not change the map
  id, the opcode, or the operand encoding of the VEX instruction.

Note: The promoted versions of MOVBE will be extended to include the “MOVBE
  reg1, reg2”.

  gas/ChangeLog:

  2023-12-28  Lingling Kong <lingling.kong@intel.com>
	      H.J. Lu  <hongjiu.lu@intel.com>
	      Lili Cui <lili.cui@intel.com>
	      Lin Hu   <lin1.hu@intel.com>

	* config/tc-i386.c (struct _i386_insn): Add has_egpr.
	(need_evex_encoding): Adjusted for apx.
	(cpu_flags_match): Ditto.
	(install_template): Handled APX combines.
	(is_apx_evex_encoding): Test apx evex encoding.
	(build_apx_evex_prefix): Enabe APX evex prefix.
	(md_assemble): Handle apx with evex encoding.
	(process_suffix): Handle apx map4 prefix.
	(check_register): Assign i.vec_encoding for APX evex instructions.
	* testsuite/gas/i386/x86-64-evex.d: Adjust test cases.
	* testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe.

opcodes/ChangeLog:

	* i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3.
	* i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0,
	PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8,
	PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB,
	PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD,
	PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF,
	PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1,
	PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8.
	* i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0.
	* i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn
	promote to apx to use gpr32
	* opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90,
	X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2,
	X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6,
	X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91.
	* i386-dis.c
	(struct instr_info): Deleted bool r.
	(PREFIX_NP_OR_DATA): New.
	(NO_PREFIX): New.
	(putop): Ditto.
	(X86_64_EVEX_FROM_VEX_TABLE): Diito.
	(get_valid_dis386): Decode insn erex in extend evex prefix.
	Handle EVEX_MAP4
	(print_insn): Handle PREFIX_DATA_AND_NP_ONLY.
	(print_register): Handle apx instructions decode.
	(OP_E_memory): Diito.
	(OP_G): Diito.
	(OP_XMM): Diito.
	(DistinctDest_Fixup): Diito.
	* i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4.
	* i386-opc.h (SPACE_EVEXMAP4): Add legacy insn
	promote to evex.
	* i386-opc.tbl: Handle some legacy and vex insns don't
	support gpr32. And add some legacy insn (map2 / 3) promote
	to evex.
2023-12-28 11:31:01 +00:00
Cui, Lili
2b1d6655c5 Created an empty EVEX_MAP4_ sub-table for EVEX instructions.
opcode/ChangeLog:

	* i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for
	legacy insn promote to EVEX insn.
	* opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28 11:21:55 +00:00
Cui, Lili
80d61d8d61 Support APX GPR32 with rex2 prefix
APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy
instructions. We added the NoEgpr flag in i386-gen.c for instructions
that do not support EGPR.

gas/ChangeLog:

2023-12-28  Lingling Kong <lingling.kong@intel.com>
	    H.J. Lu  <hongjiu.lu@intel.com>
	    Lili Cui <lili.cui@intel.com>
	    Lin Hu   <lin1.hu@intel.com>

	* config/tc-i386.c
	(enum i386_error): Add unsupported_EGPR_for_addressing
	and invalid_pseudo_prefix.
	(struct _i386_insn): Add rex2 and rex2_encoding for
	gpr32.
	(cpu_arch): Add apx_f.
	(is_cpu): Ditto.
	(register_number): Handle RegRex2 for gpr32.
	(is_apx_rex2_encoding): New func. Test rex2 prefix encoding.
	(build_rex2_prefix): New func. Build legacy insn in
	opcode 0/1 use gpr32 with rex2 prefix.
	(establish_rex): Handle rex2 and rex2_encoding.
	(optimize_encoding): Handel add r16-r31 for registers.
	(md_assemble): Handle apx encoding.
	(parse_insn): Handle Prefix_REX2.
	(check_EgprOperands): New func. Check if Egprs operands
	are valid for the instruction
	(match_template):  Handle Egpr operands check.
	(set_rex_rex2):  New func. set i.rex and i.rex2.
	(build_modrm_byte): Ditto.
	(output_insn): Handle rex2 2-byte prefix output.
	(check_register): Handle check egpr illegal without
	target apx, 64-bit mode and with rex_prefix.
	* doc/c-i386.texi: Document .apx.
	* testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d: D5 valid
	in 64-bit mode.
	* testsuite/gas/i386/ilp32/x86-64-opcode-inval.d: Ditto.
	* testsuite/gas/i386/rex-bad: Adjust rex testcase.
	* testsuite/gas/i386/x86-64-opcode-inval-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-opcode-inval.d: Ditto.
	* testsuite/gas/i386/x86-64-opcode-inval.s: Ditto.
	* testsuite/gas/i386/x86-64-pseudos-bad.l: Add illegal rex2 test.
	* testsuite/gas/i386/x86-64-pseudos-bad.s: Ditto.
	* testsuite/gas/i386/x86-64-pseudos.d: Add rex2 test.
	* testsuite/gas/i386/x86-64-pseudos.s: Ditto.
	* testsuite/gas/i386/x86-64.exp: Run APX tests.
	* testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test.
	* testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test.
	* testsuite/gas/i386/x86-64-apx-rex2.d: New test.
	* testsuite/gas/i386/x86-64-apx-rex2.s: New test.

include/ChangeLog:

	* opcode/i386.h (REX2_OPCODE): New.
	(REX2_M): Ditto.

opcodes/ChangeLog:

	* i386-dis.c (struct instr_info): Add erex for gpr32.
	Add last_erex_prefix for rex2 prefix.
	(REX2_M): Extend for gpr32.
	(PREFIX_REX2): Ditto.
	(PREFIX_REX2_ILLEGAL): Ditto.
	(ckprefix): Ditto.
	(prefix_name): Ditto.
	(print_insn): Ditto.
	(print_register): Ditto.
	(OP_E_memory): Ditto.
	(OP_REG): Ditto.
	(OP_EX): Ditto.
	* i386-gen.c (rex2_disallowed): Some instructions are not allowed rex2 prefix.
	(process_i386_opcode_modifier): Set NoEgpr for VEX and some special instructions.
	(output_i386_opcode): Handle if_entry_needs_special_handle.
	* i386-init.h : Regenerated.
	* i386-mnem.h : Regenerated.
	* i386-opc.h (enum i386_cpu): Add CpuAPX_F.
	(NoEgpr): New.
	(Prefix_NoOptimize): Ditto.
	(Prefix_REX2): Ditto.
	(RegRex2): Ditto.
	* i386-opc.tbl: Add rex2 prefix.
	* i386-reg.tbl: Add egprs (r16-r31).
	* i386-tbl.h: Regenerated.
2023-12-28 11:14:41 +00:00
Lulu Cai
26265e7fdf LoongArch: Add new relocs and macro for TLSDESC.
The normal DESC instruction sequence is:
  pcalau12i  $a0,%desc_pc_hi20(var)     #R_LARCH_TLS_DESC_PC_HI20
  addi.d     $a0,$a0,%desc_pc_lo12(var) #R_LARCH_TLS_DESC_PC_LO12
  ld.d       $ra,$a0,%desc_ld(var)	#R_LARCH_TLS_DESC_LD
  jirl       $ra,$ra,%desc_call(var)	#R_LARCH_TLS_DESC_CALL
  add.d	     $a0,$a0,$tp
2023-12-25 11:46:22 +08:00
Alan Modra
2d120f18ef Re: LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">
This fixes the buffer overflow added in commit 22b78fad28, and a few
other problems.

	* loongarch-coder.c (loongarch_split_args_by_comma): Don't
	overflow buffer when args == "".  Don't remove unbalanced
	quotes.  Don't trim last arg if max number of args exceeded.
2023-12-25 10:25:36 +10:30
Jens Remus
1c354ebcba s390: Add suffix to conditional branch instruction descriptions
Suffix the instruction description of conditional branch extended
mnemonics with their condition (e.g. "on A high"). This complements
the optional printing of instruction descriptions as comments in the
disassembly.

Due to the added text the maximum description length is increased from
80 to 128 characters (including the trailing '\0' character).

opcodes/
	* s390-mkopc.c: Add suffix to conditional branch extended
	  mnemonic instruction descriptions.

gas/
	* testsuite/gas/s390/zarch-insndesc.s: Add test cases for
	  printing of suffixed instruction description of conditional
	  branch extended mnemonics.
	* testsuite/gas/s390/zarch-insndesc.d: Likewise.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20 11:50:32 +01:00
Jens Remus
f96fe7f454 s390: Optionally print instruction description in disassembly
Print instruction description as comment in disassembly with s390
architecture specific option "insndesc":

- For objdump it can be enabled with option "-M insndesc"
- In gdb it can be enabled with "set disassembler-options insndesc"

Since comments are not column aligned the output can enhanced for
readability by postprocessing using a filter such as "expand":

... | expand -t 8,16,24,32,40,80

Or when using in combination with objdump option --visualize-jumps:

... | expand | sed -e 's/ *#/\t#/' | expand -t 1,80

Note that the instruction descriptions add about 128 KB to s390-opc.o:

s390-opc.o without instruction descriptions: 216368 bytes
s390-opc.o with instruction descriptions   : 348432 bytes

binutils/
	* NEWS: Mention new s390-specific disassembler option
	  "insndesc".

include/
	* opcode/s390.h (struct s390_opcode): Add field to hold
	  instruction description.

opcodes/
	* s390-mkopc.c: Copy instruction description from s390-opc.txt
	  into generated operation code table s390-opc.tab.
	* s390-opc.c (s390_opformats): Provide NULL as description in
	  .insn pseudo-mnemonics opcode table.
	* s390-dis.c: Add s390-specific disassembler option "insndesc"
	  and optionally print the instruction description as comment in
	  the disassembly when it is specified.

gas/
	* testsuite/gas/s390/s390.exp: Add new test disassembly test
	  case "zarch-insndesc".
	* testsuite/gas/s390/zarch-insndesc.s: New test case for s390-
	  specific disassembler option "insndesc".
	* testsuite/gas/s390/zarch-insndesc.d: Likewise.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20 11:50:32 +01:00
Jens Remus
a3fa108623 s390: Use safe string functions and length macros in s390-mkopc
Use strncpy() and snprintf() instead of strcpy() and strcat(). Define
and use macros for string lengths, such as mnemonic, instruction
format, and instruction description.

This is a mechanical change, although some buffers have increased in
length by one character. This has been confirmed by verifying that the
generated opcode/s390-opc.tab is unchanged.

opcodes/
	* s390-mkopc.c: Use strncpy() and strncat().

Suggested-by: Nick Clifton <nickc@redhat.com>
Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20 11:50:32 +01:00
Jens Remus
730e7ddc24 s390: Enhance error handling in s390-mkopc
When the s390-mkopc utility detects an error it prints an error message
to strerr and either continues processing or exists with a non-zero
return code. If it continues without detecting any further error the
final return code was zero, potentially hiding the detected error.

Introduce a global variable to hold the final return code and initialize
it to EXIT_SUCCESS. Introduce a helper function print_error() that
prints an error message to stderr and sets the final return code to
EXIT_FAILURE. Use it to print all error messages. Return the final
return code at the end of the processing.

While at it enhance error messages to state more clearly which mnemonic
an error was detected for. Also continue processing for cases where
subsequent mnemonics can be processed.

opcodes/
	* s390-mkopc.c: Enhance error handling. Return EXIT_FAILURE
	  in case of an error, otherwise EXIT_SUCCESS.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20 11:50:32 +01:00
Jens Remus
2ff609b4ce s390: Provide IBM z16 (arch14) instruction descriptions
Provide descriptions for instructions introduced with commit ba2b480f103
("IBM Z: Implement instruction set extensions"). This complements commit
69341966def ("IBM zSystems: Add support for z16 as CPU name."). Use
instruction names from IBM z/Architecture Principles of Operation [1] as
instruction description.

[1]: IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16,
     https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf

opcodes/
	* s390-opc.txt: Add descriptions for IBM z16 (arch14)
	  instructions.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20 11:50:32 +01:00
Jens Remus
8e194ff8cc s390: Align letter case of instruction descriptions
Change the bitwise operations names "and" and "or" to lower case. Change
the register name abbreviations "FPR", "GR", and "VR" to upper case.

opcodes/
	* s390-opc.txt: Align letter case of instruction descriptions.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20 11:50:32 +01:00
Jens Remus
78aa7688e8 s390: Fix build when using EXEEXT_FOR_BUILD
Suffix the s390-mkopc build utility executable file name with
EXEEXT_FOR_BUILD. Otherwise it cannot be located when building with
EXEEXT_FOR_BUILD. Use pattern used for other architecture build
utilities and compile and link s390-mkopc in two steps.

While at it also specify the dependencies of s390-mkopc.c.

opcodes/
	* Makefile.am: Add target to build s390-mkopc.o. Correct
	  target to build s390-mkopc$(EXEEXT_FOR_BUILD).
	* Makefile.in: Regenerate.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20 11:50:32 +01:00
Andrea Corallo
d645278cdf aarch64: Add FEAT_ITE support
This patch add support for FEAT_ITE "Instrumentation Extension" adding
the "trcit" instruction.

This is enabled by the +ite march flag.
2023-12-19 15:35:49 +01:00
Andrea Corallo
db168da2e0 aarch64: Add FEAT_ECBHB support
This patch add support for FEAT_ECBHB "Exploitative control using
branch history information" adding the "clrbhb" instruction.  AFAIU
the same alias was originally added as "clearbhb" before the
architecture was finalized (Mandatory v8.9-a/v9.4-a; Optional
v8.0-a+/v9.0-a+).
2023-12-19 15:35:49 +01:00
Andrea Corallo
88b5a8ae13 aarch64: Add FEAT_SPECRES2 support
This patch add supports for FEAT_SPECRES2 "Enhanced speculation
restriction instructions" adding the "cosp" instruction.

This is mandatory v8.9-a/v9.4-a and optional v8.0-a+/v9.0-a+.  It is
enabled by the +predres2 march flag.
2023-12-19 15:35:49 +01:00
Haochen Jiang
fa88a361f9 x86: Remove the restriction for size of the mask register in AVX10
Since AVX10.1/256 will also allow 64 bit mask register, we will
remove the restriction for size of the mask register in AVX10.

gas/ChangeLog:

	* config/tc-i386.c (VSZ128, VSZ256, VSZ512): New.
	(VEX_check_encoding): Remove opcode_modifier check for vsz.
	* testsuite/gas/i386/avx10-vsz.l: Remove testcases for mask
	registers since they are not needed.
	* testsuite/gas/i386/avx10-vsz.s: Ditto.

opcodes/ChangeLog:

	* i386-gen.c: Remove Vsz.
	* i386-opc.h: Ditto.
	* i386-opc.tbl: Remove kvsz.
	* i386-tbl.h: Regenerated.
2023-12-19 16:35:24 +08:00
mengqinggang
784d5a936a LoongArch: Add call36 and tail36 pseudo instructions for medium code model
For tail36, it is necessary to explicitly indicate the temporary register.
  Therefore, the compiler and users will know that the tail will use a register.

  call36 func
    pcalau18i $ra, %call36(func)
    jirl      $ra, $ra, 0;

  tail36 $t0, func
    pcalau18i $t0, %call36(func)
    jirl      $zero, $t0, 0;
2023-12-18 18:36:29 +08:00
Jan Beulich
df5a4840c4 revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR"
This reverts commit 1f865bae65db9588f6994c02a92355bfb4e3d955. The
specification is going to by updated in a way rendering this change
wrong.
2023-12-15 12:40:00 +01:00
Jan Beulich
35266cb139 x86: fold assembly dialect attributes
Now that ATTSyntax and ATTMnemonic aren't use in combination anymore,
fold them and IntelSyntax into a single, enum-like attribute. Note that
this shrinks i386_opcode_modifier back to 2 32-bit words (albeit that's
not for long, seeing in-flight additions for APX).
2023-12-15 12:05:11 +01:00
Jan Beulich
7d3182d6aa x86: Intel syntax implies Intel mnemonics
As noted in the context of d53e6b98a259 ("x86/Intel: correct disassembly
of fsub*/fdiv*") there's no such thing as Intel syntax without Intel
mnemonics. Enforce this on the assembler side, and disentangle command
line option handling on the disassembler side accordingly.

As a result in the opcode table specifying ATTMnemonic|ATTSyntax becomes
redundant with just ATTMnemonic. Drop the now meaningless ATTSyntax and
remove the then no longer accessible templates.
2023-12-15 12:04:39 +01:00
Jin Ma
8cb16b6858 RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension.
The description of instructions 'th.fmv.hw.x' and 'th.fmv.x.hw' of the
XTheadFmv extension in T-Head specific is incorrect, and it also has
some impact on the implementation of the binutils, so this patch
corrects this.

For details see:
https://github.com/T-head-Semi/thead-extension-spec/pull/34

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-fmv.d: Correct test.
	* testsuite/gas/riscv/x-thead-fmv.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_FMV_HW_X): Correct coding.
	(MASK_TH_FMV_HW_X): Likewise.
	(MATCH_TH_FMV_X_HW): Likewise.
	(MASK_TH_FMV_X_HW): Likewise.

opcodes/ChangeLog:

	* riscv-opc.c: Correct operands.
2023-12-14 09:54:19 +01:00
Cui, Lili
e20298da05 Remove redundant Byte, Word, Dword and Qword from insn templates.
opcodes/ChangeLog:

	* i386-opc.tbl: Remove redundant Byte, Word, Dword and Qword.
2023-12-14 01:56:00 +00:00
Cui, Lili
b70a487d59 Make const_1_mode print $1 in AT&T syntax
Make const_1_mode print $1 in AT&T syntax, otherwise
there will be correctness issues when it is extended
to support APX NDD,

gas/ChangeLog:

        * testsuite/gas/i386/intel.d: Adjust testcase.
        * testsuite/gas/i386/lfence-load.d: Ditto.
        * testsuite/gas/i386/noreg16-data32.d: Ditto.
        * testsuite/gas/i386/noreg16.d: Ditto.
        * testsuite/gas/i386/noreg32-data16.d: Ditto.
        * testsuite/gas/i386/noreg32.d: Ditto.
        * testsuite/gas/i386/noreg64-data16.d: Ditto.
        * testsuite/gas/i386/noreg64-rex64.d: Ditto.
        * testsuite/gas/i386/noreg64.d: Ditto.
        * testsuite/gas/i386/opcode-suffix.d: Ditto.
        * testsuite/gas/i386/opcode.d: Ditto.
        * testsuite/gas/i386/x86-64-lfence-load.d: Ditto.
        * testsuite/gas/i386/x86-64-opcode.d: Ditto.

opcodes/ChangeLog:

        * i386-dis.c (OP_I): Make const_1_mode print $1 in AT&T syntax.
2023-12-13 06:07:36 +00:00
mengqinggang
22b78fad28 LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">
Support symbol names enclosed in double quotation marks.
2023-12-11 17:54:50 +08:00
Jens Remus
c5306fed7d s390: Support for jump visualization in disassembly
Add support for jump visualization for the s390 architecture in
disassembly:

objdump -d --visualize-jumps ...

Annotate the (conditional) jump and branch relative instructions with
information required for jump visualization:
- jump: Unconditional jump / branch relative.
- condjump: Conditional jump / branch relative.
- jumpsr: Jump / branch relative to subroutine.

Unconditional jump and branch relative instructions are annotated as
jump.
Conditional jump and branch relative instructions, jump / branch
relative on count/index, and compare and jump / branch relative
instructions are annotated as condjump.
Jump and save (jas, jasl) and branch relative and save (bras, brasl)
instructions are annotated as jumpsr (jump to subroutine).

Provide instruction information required for jump visualization during
disassembly.
The instruction type is provided after determining the opcode.
For non-code it is set to dis_noninsn. Otherwise it defaults to
dis_nonbranch. No annotation is done for data reference instructions
(i.e. instruction types dis_dref and dis_dref2). Note that the
instruction type needs to be provided before printing of the
instruction, as it is used in print_address_func() to translate the
argument value into an address if it is assumed to be a PC-relative
offset. Note that this is never the case on s390, as
print_address_func() is only called with addresses and never with
offsets.
The target of the (conditional) jump and branch relative instructions
is provided during print, when the PC relative operand is decoded.

include/
	* opcode/s390.h: Define opcode flags to annotate instruction
	  class information for jump visualization:
	  S390_INSTR_FLAG_CLASS_BRANCH, S390_INSTR_FLAG_CLASS_RELATIVE,
	  S390_INSTR_FLAG_CLASS_CONDITIONAL, and
	  S390_INSTR_FLAG_CLASS_SUBROUTINE.
	  Define opcode flags mask S390_INSTR_FLAG_CLASS_MASK for above
	  instruction class information.
	  Define helpers for common instruction class flag combinations:
	  S390_INSTR_FLAGS_CLASS_JUMP, S390_INSTR_FLAGS_CLASS_CONDJUMP,
	  and S390_INSTR_FLAGS_CLASS_JUMPSR.

opcodes/
	* s390-mkopc.c: Add opcode flags to annotate information
	  for jump visualization: jump, condjump, and jumpsr.
	* s390-opc.txt: Annotate (conditional) jump and branch relative
	  instructions with information for jump visualization.
	* s390-dis.c (print_insn_s390, s390_print_insn_with_opcode):
	  Provide instruction information for jump visualization.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-04 17:13:33 +00:00
Jan Beulich
1f865bae65 x86: allow 32-bit reg to be used with U{RD,WR}MSR
... as MSR index specifier: It is unreasonable to demand that people
write less readable / understandable code, just because the present
documentation mentions only Reg64. Whether to also adjust the
disassembler is a separate question, perhaps indeed more tightly tied
to what the spec says.
2023-12-01 08:26:36 +01:00
Patrick O'Neill
2b33b0d960 RISC-V: Make riscv_is_mapping_symbol stricter
riscv_is_mapping_symbol currently accepts any symbol that starts with $x
or $d. This patch makes the check more strict, requiring exactly $x, $d,
or $xrv. It also makes use of this stricter mapping in
riscv_is_valid_mapping_symbol.

ChangeLog:

	* bfd/cpu-riscv.c (riscv_elf_is_mapping_symbols): Match only
	strings that are exactly $x, $d, or $xrv.
	* opcodes/riscv-dis.c (riscv_is_valid_mapping_symbol): Use
	riscv_elf_is_mapping_symbols.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-12-01 11:22:45 +08:00
Nelson Chu
248bf6de04 RISC-V: Add SiFive custom vector coprocessor interface instructions v1.0
SiFive has define as set of flexible instruction for extending vector
coprocessor, it able to encoding opcode like .insn but with predefined
format.

List of instructions:
  sf.vc.x
  sf.vc.i
  sf.vc.vv
  sf.vc.xv
  sf.vc.iv
  sf.vc.fv
  sf.vc.vvv
  sf.vc.xvv
  sf.vc.ivv
  sf.vc.fvv
  sf.vc.vvw
  sf.vc.xvw
  sf.vc.ivw
  sf.vc.fvw
  sf.vc.v.x
  sf.vc.v.i
  sf.vc.v.vv
  sf.vc.v.xv
  sf.vc.v.iv
  sf.vc.v.fv
  sf.vc.v.vvv
  sf.vc.v.xvv
  sf.vc.v.ivv
  sf.vc.v.fvv
  sf.vc.v.vvw
  sf.vc.v.xvw
  sf.vc.v.ivw
  sf.vc.v.fvw

Spec of Xsfvcp
https://www.sifive.com/document-file/sifive-vector-coprocessor-interface-vcix-software

Co-authored-by: Hau Hsu <hau.hsu@sifive.com>
Co-authored-by: Kito Cheng <kito.cheng@sifive.com>
2023-12-01 09:29:07 +08:00
Christoph Müllner
ea1bd00742 RISC-V: Zv*: Add support for Zvkb ISA extension
Back then when the support for the RISC-V vector crypto extensions
was merged, the specification was frozen, but not ratified.
A frozen specification is allowed to change within tight bounds
before ratification and this has happend with the vector crypto
extensions.

The following changes were applied:
* A new extension Zvkb was defined, which is a strict subset of Zvbb.
* Zvkn and Zvks include now Zvkb instead of Zvbb.

This patch implements these changes between the frozen and the
ratified specification.

Note, that this technically an incompatible change of Zvkn and Zvks,
but I am not aware of any project that depends on the currently
implemented behaviour of Zvkn and Zvks. So this patch should be fine.

Reported-By: Jerry Shih <jerry.shih@sifive.com>
Reported-By: Eric Biggers <ebiggers@kernel.org>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
2023-12-01 01:48:27 +01:00
Patrick O'Neill
460e0e6e3e RISC-V: Avoid updating state until symbol is found
Currently objdump gets and updates the map state once per symbol. Updating the
state (partiularly riscv_parse_subset) is expensive and grows quadratically
since we iterate over all symbols. By deferring this until once we've found the
symbol of interest, we can reduce the time to dump a 4k insn file of .norvc and
.rvc insns from ~47 seconds to ~0.13 seconds.

opcodes/ChangeLog:

	* riscv-dis.c (riscv_get_map_state): Remove state updating logic
	and rename to riscv_is_valid_mapping_symbol.
	(riscv_update_map_state): Add state updating logic to seperate function.
	(riscv_search_mapping_symbol): Use new riscv_update_map_state.
	(riscv_data_length): Ditto.

Signed-off-by: Patrick O'Neill <patrick@rivosinc.com>
2023-11-30 15:52:30 +08:00
Jiajie Chen
cd51849c90 as: Add new estimated reciprocal instructions in LoongArch v1.1
New estimated reciprocal instructions in LoongArch v1.1:

- frecipe.s/d
- frsqrte.s/d
- vfrecipe.s/d
- vfrsqrte.s/d
- xvfrecipe.s/d
- xvfrsqrte.s/d

Signed-off-by: Jiajie Chen <c@jia.je>
2023-11-27 15:18:15 +08:00
Jiajie Chen
9ff4752d0f as: Add new atomic instructions in LoongArch v1.1
LoongArch V1.1 release is out at
https://github.com/loongson/LoongArch-Documentation.

New atomic instructions in LoongArch v1.1:

- sc.q
- llacq.w/d
- screl.w/d
- amcas{_db}.b/h/w/d
- amswap{_db}.b/h
- amadd{_db}.b/h

Signed-off-by: Jiajie Chen <c@jia.je>
2023-11-27 15:18:09 +08:00
Jan Beulich
2ec31e54df RISC-V: drop leftover match_never() references
Commit 27b33966b18e "RISC-V: disallow x0 with certain macro-insns"
wasn't properly re-based over recent opcode table additions.
2023-11-24 10:15:59 +01:00
Jan Beulich
d3b01414b9 x86: shrink opcode sets table
Have i386-gen produce merely the offsets into i386_optab[]. Besides
allowing to shrink the table even on 32-bit builds, this results in
removing a level of indirection from the frequently accessed
current_templates, in return for adding a level of indirection when
looking up mnemonics (commonly happening just once per insn). Plus for
PIE builds of gas it also reduces the number of relocations by about two
thousand. Finally a somewhat ugly static variable can also be eliminated
from i386_displacement().
2023-11-24 09:55:51 +01:00
Jan Beulich
39bb3ade81 x86: also prefer VEX encoding over EVEX one for VCVTNEPS2BF16 when possible
Deal with what 58bceb182740 ("x86: prefer VEX encodings over EVEX ones
when possible") left out, for being slightly less straightforward.
2023-11-24 09:55:29 +01:00
Jan Beulich
eb5e952f95 RISC-V: reduce redundancy in sign/zero extension macro insn handling
Fold M_{S,Z}EXTH, deriving signed-ness from the incoming mnemonic. Fold
riscv_ext()'s calls md_assemblef(), the first of which were entirely
identical, while the other pair differed in just a single character.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-11-24 09:53:55 +01:00
Jan Beulich
27b33966b1 RISC-V: disallow x0 with certain macro-insns
While for some of the macro insns using x0 is kind of okay, as they
would merely resolve to a sequence of hint insns (and hence not cause
misbehavior at runtime), several of them have the degenerate AUIPC
followed by a load, store, or branch using other than the designated
symbol as address and hence causing runtime issues. Refuse to assemble
those, leveraging that the matching function so far wasn't really used
for macro insns: NULL is now allowed, indicating a match (which imo is
preferable over converting match_never() to match_always()), while
other matching functions now (also) used for macro insns need to avoid
calling match_opcode().

Note that for LA the restriction is slightly too strict: In non-PIC mode
using x0 would be okay-ish as per above (as it's just LLA there). Yet
libopcodes doesn't know what mode gas is presently assembling for, so we
want to err on the safe side.

Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
2023-11-24 09:53:15 +01:00
Nick Clifton
6c0c7d489b Fix building for the s390 target with clang 2023-11-24 08:10:12 +00:00
Jens Remus
6e1d1b2e7b s390: Correct prno instruction name
IBM z13 (arch11) introduced ppno (Perform Pseudorandom Number Operation).
IBM z14 (arch12) introduced prno (Perform Random Number Operation) and
deprecated ppno.

opcodes/
	* s390-opc.txt: Correct prno instruction name.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-11-23 15:51:03 +01:00
Jens Remus
2bf1f788bd s390: Add missing extended mnemonics
Add extended mnemonics specified in the z/Architecture Principles of
Operation [1] and z/Architecture Reference Summary [2], that were
previously missing from the opcode table.

The following added extended mnemonics are synonyms to a base mnemonic
and therefore disassemble into their base mnemonic:
jc, jcth, lfi, llgfi, llghi

The following added extended mnemonics are more specific than their base
mnemonic and therefore disassemble into the added extended mnemonic:
risbhgz, risblgz, rnsbgt, rosbgt, rxsbgt

The following added extended mnemonics are more specific than their base
mnemonic, but disassemble into their base mnemonic due to design
constraints:
notr, notgr

The missing extended mnemonic jl* conditional jump long flavors cannot
be added, as they would clash with the existing non-standard extended
mnemonic j* conditional jump flavors jle and jlh. The missing extended
mnemonic jlc jump long conditional is not added, as the related jl*
flavors cannot be added.
Note that these missing jl* conditional jump long flavors are already
defined as non-standard jg* flavors instead. While the related missing
extended mnemonic jlc could be added as non-standard jgc instead it is
forgone in favor of not adding further non-standard mnemonics.

The missing extended mnemonics sllhh, sllhl, slllh, srlhh, srlhl, and
srllh cannot be implemented using the current design, as they require
computed operands. For that reason the following missing extended
mnemonics are not added as well, as they fall into the same category of
instructions that operate on high and low words of registers. They
should better be added together, not to confuse the user, which of those
instructions are currently implemented or not.
lhhr, lhlr, llhfr, llchhr, llchlr, llclhr, llhhhr, llhhlr, llhlhr,
nhhr, nhlr, nlhr, ohhr, ohlr, olhr, xhhr, xhlr, xlhr

[1] IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16,
    https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf
[2] IBM z/Architecture Reference Summary, SA22-7871-11,
    https://www.ibm.com/support/pages/sites/default/files/2022-09/SA22-7871-11.pdf

opcodes/
	* s390-opc.c: Define operand formats R_CP16_28, U6_18, and
	  U5_27. Define instruction formats RIE_RRUUU3, RIE_RRUUU4,
	  and RRF_R0RR4.
	* s390-opc.txt: Add extended mnemonics jc, jcth, lfi, llgfi,
	  llghi, notgr, notr, risbhgz, risblgz, rnsbgt, rosbgt, and
	  rxsbgt.

gas/
	* config/tc-s390.c: Add support to insert operand for format
	  R_CP16_28, reusing existing logic for format V_CP16_12.
	* testsuite/gas/s390/esa-g5.s: Add test for extended mnemonic
	  jc.
	* testsuite/gas/s390/esa-g5.d: Likewise.
	* testsuite/gas/s390/zarch-z900.s: Add test for extended
	  mnemonic llghi.
	* testsuite/gas/s390/zarch-z900.d: Likewise.
	* testsuite/gas/s390/zarch-z9-109.s: Add tests for extended
	  mnemonics lfi and llgfi.
	* testsuite/gas/s390/zarch-z9-109.d: Likewise.
	* testsuite/gas/s390/zarch-z10.s: Add tests for extended
	  mnemonics rnsbgt, rosbgt, and rxsbgt.
	* testsuite/gas/s390/zarch-z10.d: Likewise.
	* testsuite/gas/s390/zarch-z196.s: Add tests for extended
	  mnemonics jcth, risbhgz, and risblgz.
	* testsuite/gas/s390/zarch-z196.d: Likewise.
	* testsuite/gas/s390/zarch-arch13.s: Add tests for extended
	  mnemonics notr and notgr.
	* testsuite/gas/s390/zarch-arch13.d: Likewise.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-11-23 15:51:03 +01:00
Jens Remus
fca086d928 s390: Align optional operand definition to specs
The IBM z/Architecture Principle of Operation [1] specifies the last
operand(s) of some (extended) mnemonics to be optional. Align the
mnemonic definitions in the opcode table according to specification.

This changes the last operand of the following (extended) mnemonics to
be optional:
risbg, risbgz, risbgn, risbgnz, risbhg, risblg, rnsbg, rosbg, rxsbg

Note that efpc and sfpc actually have only one operand, but had
erroneously been defined to have two. For backwards compatibility the
wrong RR register format must be retained. Since the superfluous second
operand is defined as optional the instruction can still be coded as
specified.

[1]: IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16,
     https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf

opcodes/
	* s390-opc.txt: Align optional operand definition to
	specification.

testsuite/
	* zarch-z10.s: Add test cases for risbg, risbgz, rnsbg, rosbg,
	  and rxsbg.
	* zarch-z10.d: Likewise.
	* zarch-z196.s: Add test cases for risbhg and risblg.
	* zarch-z196.d: Likewise.
	* zarch-zEC12.s: Add test cases for risbgn and risbgnz.
	* zarch-zEC12.d: Likewise.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-11-23 15:51:03 +01:00
Jens Remus
eeafc61979 s390: Make operand table indices relative to each other
This is a purely mechanical change. It allows subsequent insertions into
the operands table without having to renumber all operand indices.

The only differences in the resulting ELF object are in the .debug_info
section. This has been confirmed by diffing the following xxd and readelf
output:

xxd s390-opc.o
readelf -aW -x .text -x .data -x .bss -x .rodata -x .debug_info \
  -x .symtab -x .strtab -x .shstrtab --debug-dump s390-opc.o

opcodes/
	* s390-opc.c: Make operand table indices relative to each other.

Signed-off-by: Jens Remus <jremus@linux.ibm.com>
Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-11-23 15:51:03 +01:00
Jin Ma
d95ba7227e RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds permutation instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension
are documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	permutation instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VMVXS): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.
2023-11-23 09:32:18 +08:00