Change gdb_assert_not_reached to accept a format string plus
corresponding arguments. This allows giving more precise messages.
Because the format string passed by the caller is prepended with a "%s:"
to add the function name, the callers can no longer pass a translated
string (`_(...)`). Make the gdb_assert_not_reached include the _(),
just like the gdb_assert_fail macro just above.
Change-Id: Id0cfda5a57979df6cdaacaba0d55dd91ae9efee7
The current register set selection mechanism for AArch64 is static, based
on a pre-populated array of register sets.
This means that we might potentially probe register sets that are not
available. This is OK if the kernel errors out during ptrace, but probing the
tag_ctl register, for example, does not result in a ptrace error if the kernel
supports the tagged address ABI but not MTE (PR 28355).
Making the register set selection dynamic, based on feature checks, solves
this and simplifies the code a bit. It allows us to list all of the register
sets only once, and pick and choose based on HWCAP/HWCAP2 or other properties.
I plan to backport this fix to GDB 11 as well.
Bug: https://sourceware.org/bugzilla/show_bug.cgi?id=28355
In preparation for the MVE extension patch, this one refactors some of
the register-related constants we have for ARM.
Basically I'm separating counting constants from numbering constants.
For example, ARM_A1_REGNUM is a numbering constant, whereas ARM_NUM_ARG_REGS
is a counting constant.
This commit adds support to RISC-V GDB for vector registers in the
incoming target description.
The vector registers should be described in a feature called
"org.gnu.gdb.riscv.vector", and should contain the register v0 to
v31. There's no restriction on the size or type of these registers,
so the target description can set these up as it requires.
However, if the target feature is present then all of the registers
must be present, and they must all be the same size, these
requirements are, I believe, inline with the RISC-V vector extension.
The DWARF register numbers for the vector registers have been added,
and the code to map between GDB's internal numbering and the DWARF
numbering has been updated.
I have not yet added a feature/riscv/*.xml file for the vector
extension, the consequence of this is that we can't, right now, detect
vector registers on a native target, this patch is all about
supporting vectors on a remote target.
It is worth noting that I don't actually have access to a RISC-V
target with vectors, so the only testing that this patch has had has
been done using 'set tdesc filename ....' to load a target description
to which I have manually added the vector feature. This has shown
that the vector register feature can be successfully parsed, and that
the registers show up in the expected register groups.
Additionally, the RISC-V vector extension is currently at v0.10, which
is also the v1.0 draft release. However, this extension is not yet
finalised. It is possible (but unlikely I think) that the register
set could change between now and the final release of the vector
extension. If this were to happen then we would potentially end up
changing the requirements for the new org.gnu.gdb.riscv.vector
feature. I really don't think it is likely that the register set will
change this late in the process, and even if it did, changing the
feature requirements will not be a problem as far as I am
concerned (when the alternative is GDB just continues without this
feature for now).
gdb/ChangeLog:
* NEWS: Mention new target feature name.
* arch/riscv.c (riscv_create_target_description): GDB doesn't
currently create target descriptions containing vector registers.
* arch/riscv.h (struct riscv_gdbarch_features) <vlen>: New member
variable.
<operator==>: Also compare vlen.
<hash>: Also include vlen.
* riscv-tdep.c (riscv_feature_name_vector): New static global.
(struct riscv_vector_feature): New struct.
(riscv_vector_feature): New static global.
(riscv_register_reggroup_p): Ensure vector registers are part of
the 'all' group, and part of the 'vector' group.
(riscv_dwarf_reg_to_regnum): Handle vector registers.
(riscv_gdbarch_init): Check vector register feature.
* riscv-tdep.h: Add vector registers to GDB's internal register
numbers, and to the DWARF register numbers.
gdb/doc/ChangeLog:
* gdb.texinfo (RISC-V Features): Mention vector register feature.
When we want to fetch tags from a memory range, the last address in that
range is not included.
There is a off-by-one error in aarch64_mte_get_tag_granules, which this
patch fixes.
gdb/ChangeLog:
2021-05-13 Luis Machado <luis.machado@linaro.org>
* arch/aarch64-mte-linux.c (aarch64_mte_get_tag_granules): Don't
include the last address in the range.
Whenever a memory tag violation occurs, we get a SIGSEGV. Additional
information can be obtained through the siginfo data structure.
For AArch64 the Linux kernel may expose the fault address and tag
information, if we have a synchronous event. Otherwise there is
no fault address available.
The synchronous event looks like this:
--
(gdb) continue
Continuing.
Program received signal SIGSEGV, Segmentation fault
Memory tag violation while accessing address 0x0500fffff7ff8000
Allocation tag 0x1.
Logical tag 0x5
--
The asynchronous event looks like this:
--
(gdb) continue
Continuing.
Program received signal SIGSEGV, Segmentation fault
Memory tag violation
Fault address unavailable.
--
gdb/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* aarch64-linux-tdep.c
(aarch64_linux_report_signal_info): New function.
(aarch64_linux_init_abi): Register
aarch64_linux_report_signal_info as the report_signal_info hook.
* arch/aarch64-linux.h (SEGV_MTEAERR): Define.
(SEGV_MTESERR): Define.
The patch implements the memory tagging target hooks for AArch64, so we
can handle MTE.
gdb/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* Makefile.in (ALL_64_TARGET_OBS): Add arch/aarch64-mte-linux.o.
(HFILES_NO_SRCDIR): Add arch/aarch64-mte-linux.h and
nat/aarch64-mte-linux-ptrace.h.
* aarch64-linux-nat.c: Include nat/aarch64-mte-linux-ptrace.h.
(aarch64_linux_nat_target) <supports_memory_tagging>: New method
override.
<fetch_memtags>: New method override.
<store_memtags>: New method override.
(aarch64_linux_nat_target::supports_memory_tagging): New method.
(aarch64_linux_nat_target::fetch_memtags): New method.
(aarch64_linux_nat_target::store_memtags): New method.
* arch/aarch64-mte-linux.c: New file.
* arch/aarch64-mte-linux.h: Include gdbsupport/common-defs.h.
(AARCH64_MTE_GRANULE_SIZE): Define.
(aarch64_memtag_type): New enum.
(aarch64_mte_get_tag_granules): New prototype.
* configure.nat (NATDEPFILES): Add nat/aarch64-mte-linux-ptrace.o.
* configure.tgt (aarch64*-*-linux*): Add arch/aarch64-mte-linux.o.
* nat/aarch64-mte-linux-ptrace.c: New file.
* nat/aarch64-mte-linux-ptrace.h: New file.
AArch64 MTE support in the Linux kernel exposes a new register
through ptrace. This patch adds the required code to support it.
include/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* elf/common.h (NT_ARM_TAGGED_ADDR_CTRL): Define.
gdb/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* aarch64-linux-nat.c (fetch_mteregs_from_thread): New function.
(store_mteregs_to_thread): New function.
(aarch64_linux_nat_target::fetch_registers): Update to call
fetch_mteregs_from_thread.
(aarch64_linux_nat_target::store_registers): Update to call
store_mteregs_to_thread.
* aarch64-tdep.c (aarch64_mte_register_names): New struct.
(aarch64_cannot_store_register): Handle MTE registers.
(aarch64_gdbarch_init): Initialize and setup MTE registers.
* aarch64-tdep.h (gdbarch_tdep) <mte_reg_base>: New field.
<has_mte>: New method.
* arch/aarch64-linux.h (AARCH64_LINUX_SIZEOF_MTE): Define.
gdbserver/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* linux-aarch64-low.cc (aarch64_fill_mteregset): New function.
(aarch64_store_mteregset): New function.
(aarch64_regsets): Add MTE register set entry.
(aarch64_sve_regsets): Add MTE register set entry.
This patch adds a target description and feature "mte" for aarch64.
It includes one new register, tag_ctl, that can be used to configure the
tag generation rules and sync/async modes. It is 64-bit in size.
The patch also adjusts the code that creates the target descriptions at
runtime based on CPU feature checks.
gdb/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* aarch64-linux-nat.c
(aarch64_linux_nat_target::read_description): Take MTE flag into
account.
Slight refactor to hwcap flag checking.
* aarch64-linux-tdep.c
(aarch64_linux_core_read_description): Likewise.
* aarch64-tdep.c (tdesc_aarch64_list): Add one more dimension for
MTE.
(aarch64_read_description): Add mte_p parameter and update to use it.
Update the documentation.
(aarch64_gdbarch_init): Update call to aarch64_read_description.
* aarch64-tdep.h (aarch64_read_description): Add mte_p parameter.
* arch/aarch64.c: Include ../features/aarch64-mte.c.
(aarch64_create_target_description): Add mte_p parameter and update
the code to use it.
* arch/aarch64.h (aarch64_create_target_description): Add mte_p
parameter.
* features/Makefile (FEATURE_XMLFILES): Add aarch64-mte.xml.
* features/aarch64-mte.c: New file, generated.
* features/aarch64-mte.xml: New file.
gdbserver/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* linux-aarch64-ipa.cc (get_ipa_tdesc): Update call to
aarch64_linux_read_description.
(initialize_low_tracepoint): Likewise.
* linux-aarch64-low.cc (aarch64_target::low_arch_setup): Take MTE flag
into account.
* linux-aarch64-tdesc.cc (tdesc_aarch64_list): Add one more dimension
for MTE.
(aarch64_linux_read_description): Add mte_p parameter and update to
use it.
* linux-aarch64-tdesc.h (aarch64_linux_read_description): Add mte_p
parameter.
This patch is a preparation for the next patches implementing MTE. It just adds
a HWCAP2 constant for MTE, creates a new generic arch/aarch64-mte-linux.h file
and includes that file in the source files that will use it.
gdb/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* Makefile.in (HFILES_NO_SRCDIR): Add arch/aarch64-mte-linux.h.
* aarch64-linux-nat.c: Include arch/aarch64-mte-linux.h.
* aarch64-linux-tdep.c: Likewise
* arch/aarch64-mte-linux.h: New file.
gdbserver/ChangeLog:
2021-03-24 Luis Machado <luis.machado@linaro.org>
* linux-aarch64-low.cc: Include arch/aarch64-mte-linux.h.
Enable displaced stepping over a BR/BLR instruction
Displaced stepping over an instruction executes a instruction in a
scratch area and then manually fixes up the PC address to leave
execution where it would have been if the instruction were in its
original location.
The BR instruction does not need modification in order to run correctly
at a different address, but the displaced step fixup method should not
manually adjust the PC since the BR instruction sets that value already.
The BLR instruction should also avoid such a fixup, but must also have
the link register modified to point to just after the original code
location rather than back to the scratch location.
This patch adds the above functionality.
We add this functionality by modifying aarch64_displaced_step_others
rather than by adding a new visitor method to aarch64_insn_visitor.
We choose this since it seems that visitor approach is designed
specifically for PC relative instructions (which must always be modified
when executed in a different location).
It seems that the BR and BLR instructions are more like the RET
instruction which is already handled specially in
aarch64_displaced_step_others.
This also means the gdbserver code to relocate an instruction when
creating a fast tracepoint does not need to be modified, since nothing
special is needed for the BR and BLR instructions there.
Regression tests showed nothing untoward on native aarch64 (though it
took a while for me to get the testcase to account for PIE).
------#####
Original observed (mis)behaviour before was that displaced stepping over
a BR or BLR instruction would not execute the function they called.
Most easily seen by putting a breakpoint with a condition on such an
instruction and a print statement in the functions they called.
When run with the breakpoint enabled the function is not called and
"numargs called" is not printed.
When run with the breakpoint disabled the function is called and the
message is printed.
--- GDB Session
~ [15:57:14] % gdb ../using-blr
Reading symbols from ../using-blr...done.
(gdb) disassemble blr_call_value
Dump of assembler code for function blr_call_value:
...
0x0000000000400560 <+28>: blr x2
...
0x00000000004005b8 <+116>: ret
End of assembler dump.
(gdb) break *0x0000000000400560
Breakpoint 1 at 0x400560: file ../using-blr.c, line 22.
(gdb) condition 1 10 == 0
(gdb) run
Starting program: /home/matmal01/using-blr
[Inferior 1 (process 33279) exited with code 012]
(gdb) disable 1
(gdb) run
Starting program: /home/matmal01/using-blr
numargs called
[Inferior 1 (process 33289) exited with code 012]
(gdb)
Test program:
---- using-blr ----
\#include <stdio.h>
typedef int (foo) (int, int);
typedef void (bar) (int, int);
struct sls_testclass {
foo *x;
bar *y;
int left;
int right;
};
__attribute__ ((noinline))
int blr_call_value (struct sls_testclass x)
{
int retval = x.x(x.left, x.right);
if (retval % 10)
return 100;
return 9;
}
__attribute__ ((noinline))
int blr_call (struct sls_testclass x)
{
x.y(x.left, x.right);
if (x.left % 10)
return 100;
return 9;
}
int
numargs (__attribute__ ((unused)) int left, __attribute__ ((unused)) int right)
{
printf("numargs called\n");
return 10;
}
void
altfunc (__attribute__ ((unused)) int left, __attribute__ ((unused)) int right)
{
printf("altfunc called\n");
}
int main(int argc, char **argv)
{
struct sls_testclass x = { .x = numargs, .y = altfunc, .left = 1, .right = 2 };
if (argc > 2)
{
blr_call (x);
}
else
blr_call_value (x);
return 10;
}
I haven't tried this on an actual aarch64 machine, but I am able to
exercise it like this:
(gdb) set debug aarch64
(gdb) maintenance selftest aa
Running selftest aarch64-analyze-prologue.
[aarch64] aarch64_analyze_prologue: prologue analysis gave up addr=0x14 opcode=0xf94013e0
Running selftest aarch64-process-record.
Ran 2 unit tests, 0 failed
gdb/ChangeLog:
* arch/aarch64-insn.h (aarch64_debug_printf): New.
* arch/aarch64-insn.c: Use aarch64_debug_printf.
* aarch64-tdep.c: Use aarch64_debug_printf.
Change-Id: Ifdb40e2816ab8e55a9aabb066d1833d9b5a46094
This commits the result of running gdb/copyright.py as per our Start
of New Year procedure...
gdb/ChangeLog
Update copyright year range in copyright header of all GDB files.
The FPSIMD dump in signal frames and ptrace FPSIMD dump in the SVE context
structure follows the target endianness, whereas the SVE dumps are
endianness-independent (LE).
Therefore, when the system is in BE mode, we need to reverse the bytes
for the FPSIMD data.
Given the V registers are larger than 64-bit, I've added a way for value
bytes to be set, as opposed to passing a 64-bit fixed quantity. This fits
nicely with the unwinding *_got_bytes function and makes the trad-frame
more flexible and capable of saving larger registers.
The memory for the bytes is allocated via the frame obstack, so it gets freed
after we're done inspecting the frame.
gdb/ChangeLog:
2020-12-10 Luis Machado <luis.machado@linaro.org>
* aarch64-linux-tdep.c (aarch64_linux_restore_vreg) New function.
(aarch64_linux_sigframe_init): Call aarch64_linux_restore_vreg.
* aarch64-tdep.h (V_REGISTER_SIZE): Move to ...
* arch/aarch64.h: ... here.
* nat/aarch64-sve-linux-ptrace.c: Include endian.h.
(aarch64_maybe_swab128): New function.
(aarch64_sve_regs_copy_to_reg_buf)
(aarch64_sve_regs_copy_from_reg_buf): Adjust FPSIMD entries.
* trad-frame.c (trad_frame_reset_saved_regs): Initialize
the data field.
(TF_REG_VALUE_BYTES): New enum value.
(trad_frame_value_bytes_p): New function.
(trad_frame_set_value_bytes): New function.
(trad_frame_set_reg_value_bytes): New function.
(trad_frame_get_prev_register): Handle register values saved as bytes.
* trad-frame.h (trad_frame_set_reg_value_bytes): New prototype.
(struct trad_frame_saved_reg) <data>: New field.
(trad_frame_set_value_bytes): New prototype.
(trad_frame_value_bytes_p): New prototype.
When UBSan is enabled, I noticed runtime errors complaining of shifting
of negative numbers.
This patch fixes this by reusing existing macros from the ARM port.
It also removes unused macros from AArch64's port.
gdb/ChangeLog:
2020-12-04 Luis Machado <luis.machado@linaro.org>
* aarch64-tdep.c (submask, bit, bits): Remove.
* arch/aarch64-insn.c (extract_signed_bitfield): Remove.
(aarch64_decode_adr, aarch64_decode_b aarch64_decode_bcond)
(aarch64_decode_cb, aarch64_decode_tb)
(aarch64_decode_ldr_literal): Use sbits to extract a signed
immediate.
* arch/aarch64-insn.h (submask, bits, bit, sbits): New macros.
This commit started as adding rv32e support to gdb. The rv32e
architecture is a cut-down rv32i, it only has 16 x-registers compared
to the usual 32, and an rv32e target should not have any floating
point registers.
In order to add this I needed to adjust the target description
validation checks that are performed from riscv_gdbarch_init, and I
finally got fed up with the current scheme of doing these checks and
rewrote this code.
Unfortunately the rv32e changes are currently mixed in with the
rewrite of the validation scheme. I could split these apart if anyone
is really interested in seeing these two ideas as separate patches.
The main idea behind this change is that where previously I tried to
have a purely data driven approach, a set of tables one for each
expected feature, and then a single generic function that would
validate a feature given a table, I have created a new class for each
feature. Each class has its own check member function which allows
the logic for how to check each feature to be different. I think the
new scheme is much easier to follow.
There are some other changes that I made to the validation code as
part of this commit.
I've relaxed some of the checks related to the floating point CSRs.
Previously the 3 CSRs fflags, frm, and fcsr all had to be present in
either the fpu feature or the csr feature. This requirement is now
relaxed, if the CSRs are not present then gdb will not reject the
target description. My thinking here is that there's no gdb
functionality that specifically requires these registers, and so, if a
target offers a description without these registers nothing else in
gdb should stop working.
And as part of the rv32e support targets now only have to provide the
first 16 x-registers and $pc. The second half of the x-registers (x16
-> x31) are now optional.
gdb/ChangeLog:
* arch/riscv.c: Include 'rv32e-xregs.c'.
(riscv_create_target_description): Update to handle rv32e.
* arch/riscv.h (struct riscv_gdbarch_features) <embedded>: New
member variable.
<operator==>: Update to account for new field.
<hash>: Likewise.
* features/Makefile (FEATURE_XMLFILES): Add riscv/rv32e-xregs.xml.
* features/riscv/rv32e-xregs.c: Generated.
* features/riscv/rv32e-xregs.xml: New file.
* riscv-tdep.c (riscv_debug_breakpoints): Move from later in the
file.
(riscv_debug_infcall): Likewise.
(riscv_debug_unwinder): Likewise.
(riscv_debug_gdbarch): Likewise.
(enum riscv_register_required_status): Delete.
(struct riscv_register_feature): Add constructor, delete default
constructor, copy, and assign constructors.
(struct riscv_register_feature::register_info) <required>: Delete.
<check>: Update comment and arguments.
(struct riscv_register_feature) <name>: Change to member function.
<prefer_first_name>: Delete.
<tdesc_feature>: New member function.
<registers>: Rename to...
<m_registers>: ...this.
<m_feature_name>: New member variable.
(riscv_register_feature::register_info::check): Update arguments.
(riscv_xreg_feature): Rewrite as class, create a single static
instance of the class.
(riscv_freg_feature): Likewise.
(riscv_virtual_feature): Likewise.
(riscv_csr_feature): Likewise.
(riscv_create_csr_aliases): Has become a member function inside
riscv_csr_feature class.
(riscv_abi_embedded): New function definition.
(riscv_register_name): Adjust to use new feature objects.
(struct riscv_call_info) <riscv_call_info>: Check for rv32e abi,
and adjust available argument registers.
(riscv_features_from_gdbarch_info): Check for EF_RISCV_RVE flag.
(riscv_check_tdesc_feature): Delete.
(riscv_tdesc_unknown_reg): Adjust to use new feature objects.
(riscv_gdbarch_init): Delete target description checking code, and
instead call to the new feature objects to perform the checks.
Reorder handling of no abi information case, allows small code
simplification.
(_initialize_riscv_tdep): Remove call, this is now done in the
riscv_csr_feature constructor.
* riscv-tdep.h (riscv_abi_embedded): Declare.
After commit:
commit 51a948fdf0e14fb69ab9e0c79ae8b2415801f9a3
Date: Mon Jul 20 14:18:04 2020 +0100
gdb: Have allocate_target_description return a unique_ptr
There were a few places where we could (should?) have delayed
releasing the target_desc_up until a little later. This commit
catches these cases.
In the case of ARC, the target_desc_up is now exposed right out to
gdbserver, which means making a small change there too.
There should be no user visible changes after this commit.
gdb/ChangeLog:
* arch/aarch32.c (aarch32_create_target_description): Release the
target_desc_up as late as possible.
* arch/aarch64.c (aarch64_create_target_description): Likewise.
* arch/amd64.c (amd64_create_target_description): Likewise.
* arch/arc.c (arc_create_target_description): Return a
target_desc_up, don't release it.
* arch/arc.h (arc_create_target_description): Update declaration.
(arc_lookup_target_description): Move target_desc_up into the
cache, and return a borrowed pointer.
* arch/arm.c (arm_create_target_description): Release the
target_desc_up as late as possible.
* arch/i386.c (i386_create_target_description): Likewise.
* arch/riscv.h (riscv_create_target_description): Update
declaration to match definition.
* arch/tic6x.c (tic6x_create_target_description): Release the
target_desc_up as late as possible.
gdbserver/ChangeLog:
* linux-arc-low.cc (arc_linux_read_description): Release the
unique_ptr returned from arc_create_target_description.
"arc_gdbarch_features" is a data structure containing information
about the ARC architecture: ISA version, register size, etc.
This name is misleading, because although it carries the phrase
"gdbarch", it has nothing to do with the type/interface in GDB.
Traditionaly, "gdbarch" structures are only used for that purpose.
To rectify this, this patch changes the name to "arc_arch_features".
gdb/ChangeLog:
* arch/arc.h: Rename "arc_gdbarch_features" to
"arc_arch_features".
* arc-tdep.h: Likewise.
* arc-tdep.c: Likewise.
A few changes have been made to make the register support simpler,
more flexible and extendible. The trigger for most of these changes
are the remarks [1] made earlier for v2 of this patch. The noticeable
improvements are:
- The arc XML target features are placed under gdb/features/arc
- There are two cores (based on ISA) and one auxiliary feature:
v1-core: ARC600, ARC601, ARC700
v2-core: ARC EM, ARC HS
aux: common in both
- The XML target features represent a minimalistic sane set of
registers irrespective of application (baremetal or linux).
- A concept of "feature" class has been introduced in the code.
The "feature" object is constructed from BFD and GDBARCH data.
It contains necessary information (ISA and register size) to
determine which XML target feature to use.
- A new structure (ARC_REGISTER_FEATURE) is added that allows
providing index, names, and the necessity of registers. This
simplifies the sanity checks and future extendibility.
- Documnetation has been updated to reflect ARC features better.
- Although the feature names has changed, there still exists
backward compatibility with older names through
find_obsolete_[core,aux]_names() functions.
The last two points were inspired from RiscV port.
[1]
https://sourceware.org/pipermail/gdb-patches/2020-May/168511.html
gdb/ChangeLog:
* arch/arc.h
(arc_gdbarch_features): New class to stir the selection of target XML.
(arc_create_target_description): Use FEATURES to choose XML target.
(arc_lookup_target_description): Use arc_create_target_description
to create _new_ target descriptions or return the already created
ones if the FEATURES is the same.
* arch/arc.c: Implementation of prototypes described above.
* gdb/arc-tdep.h (arc_regnum enum): Add more registers.
(arc_gdbarch_features_init): Initialize the FEATURES struct.
* arc-tdep.c (*_feature_name): Make feature names consistent.
(arc_register_feature): A new struct to hold information about
registers of a particular target/feature.
(arc_check_tdesc_feature): Check if XML provides registers in
compliance with ARC_REGISTER_FEATURE structs.
(arc_update_acc_reg_names): Add aliases for r58 and r59.
(determine_*_reg_feature_set): Which feature name to look for.
(arc_gdbarch_features_init): Given MACH and ABFD, initialize FEATURES.
(mach_type_to_arc_isa): Convert from a set of binutils machine types
to expected ISA enums to be used in arc_gdbarch_features structs.
* features/Makefile (FEATURE_XMLFILES): Add new files.
* gdb/features/arc/v1-aux.c: New file.
* gdb/features/arc/v1-aux.xml: Likewise.
* gdb/features/arc/v1-core.c: Likewise.
* gdb/features/arc/v1-core.xml: Likewise.
* gdb/features/arc/v2-aux.c: Likewise.
* gdb/features/arc/v2-aux.xml: Likewise.
* gdb/features/arc/v2-core.c: Likewise.
* gdb/features/arc/v2-core.xml: Likewise.
* NEWS (Changes since GDB 9): Announce obsolence of old feature names.
gdb/doc/ChangeLog:
* gdb.texinfo (Synopsys ARC): Update the documentation for ARC
Features.
gdb/testsuite/ChangeLog:
* gdb.arch/arc-tdesc-cpu.xml: Use new feature names.
When building gdb on x86_64-linux with --enable-targets riscv64-suse-linux, I
run into:
...
src/gdb/arch/riscv.c:112:45: required from here
/usr/include/c++/4.8/bits/hashtable_policy.h:195:39: error: no matching \
function for call to 'std::pair<const riscv_gdbarch_features, const \
std::unique_ptr<target_desc, target_desc_deleter> >::pair(const \
riscv_gdbarch_features&, target_desc*&)'
: _M_v(std::forward<_Args>(__args)...) { }
^
...
for this code in riscv_lookup_target_description:
...
/* Add to the cache. */
riscv_tdesc_cache.emplace (features, tdesc);
...
Work around this compiler problem (filed as PR gcc/96537), similar to how that
was done in commit 6d0cf4464e "Fix build with gcc-4.8.x":
...
- riscv_tdesc_cache.emplace (features, tdesc);
+ riscv_tdesc_cache.emplace (features, target_desc_up (tdesc));
...
That is, call the target_desc_up constructor explictly instead of implicitly.
Also, work around a similar issue in get_thread_arch_aspace_regcache.
Build on x86_64-linux with --enable-targets riscv64-suse-linux, and
reg-tested.
gdb/ChangeLog:
2020-08-08 Tom de Vries <tdevries@suse.de>
PR build/26344
* arch/riscv.c (riscv_lookup_target_description): Use an explicit
constructor.
* regcache.c (get_thread_arch_aspace_regcache): Same.
It was pointed out on IRC that the RISC-V target allocates target
descriptions and stores them in a global map, and doesn't delete these
target descriptions when GDB shuts down.
This isn't a particular problem, the total number of target
descriptions we can create is very limited so creating these on demand
and holding them for the entire run on GDB seems reasonable.
However, not deleting these objects on GDB exit means extra warnings
are printed from tools like valgrind, and the address sanitiser,
making it harder to spot real issues. As it's reasonably easy to have
GDB correctly delete these objects on exit, lets just do that.
I started by noticing that we already have a target_desc_up type, a
wrapper around unique_ptr that calls a function that will correctly
delete target descriptions, so I want to use that, but....
...that type is declared in gdb/target-descriptions.h. If I try to
include that file in gdb/arch/riscv.c I run into a problem, that file
is compiled into both GDB and GDBServer.
OK, I could guard the include with #ifdef, but surely we can do
better.
So then I decided to move the target_desc_up type into
gdbsupport/tdesc.h, this is the interface file for generic code shared
between GDB and GDBserver (relating to target descriptions). The
actual implementation for the delete function still lives in
gdb/target-description.c, but now gdb/arch/riscv.c can see the
declaration. Problem solved....
... but, though RISC-V doesn't use it I've now exposed the
target_desc_up type to gdbserver, so in future someone _might_ start
using it, which is fine, except right now there's no definition of the
delete function - remember the delete I used is only defined in GDB
code.
No problem, I add an implementation of the delete operator into
gdbserver/tdesc.cc, and all is good..... except....
I start getting this error from GCC:
tdesc.cc:109:10: error: deleting object of polymorphic class type ‘target_desc’ which has non-virtual destructor might cause undefined behavior [-Werror=delete-non-virtual-dtor]
Which is caused because gdbserver's target_desc type inherits from
tdesc_element which has a virtual method, and so GCC worries that
target_desc might be used as a base class.
The solution is to declare gdbserver's target_desc class as final.
This is fine so long as we never intent to inherit from
target_desc (in gdbserver). But if we did then we'd want to make
target_desc's destructor virtual anyway, so the error above would be
resolved, and there wouldn't be an issue.
gdb/ChangeLog:
* arch/riscv.c (riscv_tdesc_cache): Change map type.
(riscv_lookup_target_description): Return pointer out of
unique_ptr.
* target-descriptions.c (allocate_target_description): Add
comment.
(target_desc_deleter::operator()): Likewise.
* target-descriptions.h (struct target_desc_deleter): Moved to
gdbsupport/tdesc.h.
(target_desc_up): Likewise.
gdbserver/ChangeLog:
* tdesc.cc (allocate_target_description): Add header comment.
(target_desc_deleter::operator()): New function.
* tdesc.h (struct target_desc): Declare as final.
gdbsupport/ChangeLog:
* tdesc.h (struct target_desc_deleter): Moved here
from gdb/target-descriptions.h, extend comment.
(target_desc_up): Likewise.
This patch replaces usage of target descriptions in ARC, where the whole
description is fixed in XML, with new target descriptions where XML describes
individual features, and GDB assembles those features into actual target
description.
v2:
Removed arc.c from ALLDEPFILES in gdb/Makefile.in.
Removed vim modeline from arc-tdep.c to have it in a separate patch.
Removed braces from one line "if/else".
Undid the type change for "jb_pc" (kept it as "int").
Joined the unnecessary line breaks into one line.
No more moving around arm targets in gdb/features/Makefile.
Changed pattern checking for ARC features from "arc/{aux,core}" to "arc/".
v3:
Added include gaurds to arc.h.
Added arc_read_description to _create_ target descriptions less.
v4:
Got rid of ARC_SYS_TYPE_NONE.
Renamed ARC_SYS_TYPE_INVALID to ARC_SYS_TYPE_NUM.
Fixed a few indentations/curly braces.
Converted arc_sys_type_to_str from a macro to an inline function.
gdb/ChangeLog:
2020-03-16 Anton Kolesov <anton.kolesov@synopsys.com>
Shahab Vahedi <shahab@synopsys.com>
* Makefile.in: Add arch/arc.o
* configure.tgt: Likewise.
* arc-tdep.c (arc_tdesc_init): Use arc_read_description.
(_initialize_arc_tdep): Don't initialize old target descriptions.
(arc_read_description): New function to cache target descriptions.
* arc-tdep.h (arc_read_description): Add proto type.
* arch/arc.c: New file.
* arch/arc.h: Likewise.
* features/Makefile: Replace old target descriptions with new.
* features/arc-arcompact.c: Remove.
* features/arc-arcompact.xml: Likewise.
* features/arc-v2.c: Likewise
* features/arc-v2.xml: Likewise
* features/arc/aux-arcompact.xml: New file.
* features/arc/aux-v2.xml: Likewise.
* features/arc/core-arcompact.xml: Likewise.
* features/arc/core-v2.xml: Likewise.
* features/arc/aux-arcompact.c: Generate.
* features/arc/aux-v2.c: Likewise.
* features/arc/core-arcompact.c: Likewise.
* features/arc/core-v2.c: Likewise.
* target-descriptions (maint_print_c_tdesc_cmd): Support ARC features.
In preparation for adding the RISC-V gdbserver, this commit
restructures the API for looking up target descriptions.
The current API is riscv_create_target_description, which creates a
target description from a riscv_gdbarch_features, but also caches the
created target descriptions so that for a given features object we
always get back the same target description object. This is important
for GDB due to the way gdbarch objects are reused.
As the same target description is always returned to GDB, and can be
returned multiple times, it is returned as a const, however, the
current cache actually stores a non-const target description. This is
improved in this patch so that the cache holds a const target
description.
For gdbsever, this caching of the target descriptions is not needed,
the gdbserver looks up one target description to describe the target
it is actually running on and that is it. Further the gdbserver
actually needs to modify the target description that is looked up, so
for the gdbsever, returning a const target description is not
acceptable.
This commit aims to address this by creating two parallel target
description APIs, on is the old riscv_create_target_description,
however, this no longer performs any caching, and just creates a new
target description, and returns it as non-const.
The second API is riscv_lookup_target_description, this one performs
the caching, and calls riscv_create_target_description to create a
target description when needed.
In order to make sure the correct API is used in the correct place I
have guarded the code using the GDBSERVER define. For GDB the
riscv_create_target_description is static, and not generally usable
throughout GDB, only the lookup API is global. In gdbserver, the
lookup functions, and the cache are not defined or created at all,
only the riscv_create_target_description API is available.
There should be no user visible changes after this commit.
gdb/ChangeLog:
* arch/riscv.c (struct riscv_gdbarch_features_hasher): Only define
if GDBSERVER is not defined.
(riscv_tdesc_cache): Likewise, also store const target_desc.
(STATIC_IN_GDB): Define.
(riscv_create_target_description): Update declaration with
STATIC_IN_GDB.
(riscv_lookup_target_description): New function, only define if
GDBSERVER is not defined.
* arch/riscv.h (riscv_create_target_description): Declare only
when GDBSERVER is defined.
(riscv_lookup_target_description): New declaration when GDBSERVER
is not defined.
* nat/riscv-linux-tdesc.c (riscv_linux_read_description): Rename to...
(riscv_linux_read_features): ...this, and return
riscv_gdbarch_features instead of target_desc.
* nat/riscv-linux-tdesc.h: Include 'arch/riscv.h'.
(riscv_linux_read_description): Rename to...
(riscv_linux_read_features): ...this.
* riscv-linux-nat.c (riscv_linux_nat_target::read_description):
Update to use riscv_gdbarch_features and
riscv_lookup_target_description.
* riscv-tdep.c (riscv_find_default_target_description): Use
riscv_lookup_target_description instead of
riscv_create_target_description.
For a fix I intend to submit, I would need a function that counts the
number of set bits in a word. There is __builtin_popcount that is
supported by gcc and clang, but there is also a gnulib module that wraps
that and provides a fallback for other compilers, so I think it would be
good to use it.
I also noticed that there is a bitcount function in arch/arm.c, so I
thought that as a first step I would replace that one with the gnulib
count-one-bits module. This is what this patch does.
The gnulib module provides multiple functions, with various parameter
length (unsigned int, unsigned long int, unsigned long long int), I
chose the one that made sense for each call site based on the argument
type.
gnulib/ChangeLog:
* update-gnulib.sh (IMPORTED_GNULIB_MODULES): Import
count-one-bits module.
* configure: Re-generate.
* aclocal.m4: Re-generate.
* Makefile.in: Re-generate.
* import/count-one-bits.c: New file.
* import/count-one-bits.h: New file.
* import/Makefile.am: Re-generate.
* import/Makefile.in: Re-generate.
* import/m4/gnulib-cache.m4: Re-generate.
* import/m4/gnulib-comp.m4: Re-generate.
* import/m4/count-one-bits.m4: New file.
gdb/ChangeLog:
* arm-tdep.c: Include count-one-bits.h.
(cleanup_block_store_pc): Use count_one_bits.
(cleanup_block_load_pc): Use count_one_bits.
(arm_copy_block_xfer): Use count_one_bits.
(thumb2_copy_block_xfer): Use count_one_bits.
(thumb_copy_pop_pc_16bit): Use count_one_bits.
* arch/arm-get-next-pcs.c: Include count-one-bits.h.
(thumb_get_next_pcs_raw): Use count_one_bits.
(arm_get_next_pcs_raw): Use count_one_bits_l.
* arch/arm.c (bitcount): Remove.
* arch/arm.h (bitcount): Remove.
These are for the obsolete FPA architecture.
gdb/ChangeLog:
2020-02-11 Christian Biesinger <cbiesinger@google.com>
* arch/arm.h (enum gdb_regnum): Add comment for the FP0..7
registers.
Change-Id: I6920616318ee637493d4ca12b91fa2ebcd103d76
In arm arm_create_target_description and
aarch32_create_target_description create feature based target descriptions
instead of returning the old style descriptions.
Ensure the descriptions are created in exactly the same way as the old xml
files.
Remove the old initialize calls.
gdb/ChangeLog:
* arch/aarch32.c (aarch32_create_target_description): Create
target descriptions using features.
* arch/arm.c (arm_create_target_description)
(arm_create_mprofile_target_description): Likewise.
* arm-tdep.c (_initialize_arm_tdep): Remove tdesc init calls.
Switch the Arm target to get target descriptions via arm_read_description
and aarch32_read_description, in the same style as other feature targets.
Add an enum to specify the different types - this will also be of use to
gdbserver in a later patch.
Under the hood return the same existing pre-feature target descriptions.
gdb/ChangeLog:
* Makefile.in: Add new files.
* aarch32-tdep.c: New file.
* aarch32-tdep.h: New file.
* aarch64-linux-nat.c (aarch64_linux_nat_target::read_description):
Call aarch32_read_description.
* arch/aarch32.c: New file.
* arch/aarch32.h: New file.
* arch/arm.c (arm_create_target_description)
(arm_create_mprofile_target_description): New function.
* arch/arm.h (arm_fp_type, arm_m_profile_type): New enum.
(arm_create_target_description)
(arm_create_mprofile_target_description): New declaration.
* arm-fbsd-tdep.c (arm_fbsd_read_description_auxv): Call
read_description functions.
* arm-linux-nat.c (arm_linux_nat_target::read_description):
Likewise.
* arm-linux-tdep.c (arm_linux_core_read_description): Likewise.
* arm-tdep.c (tdesc_arm_list): New variable.
(arm_register_g_packet_guesses): Call create description functions.
(arm_read_description) (arm_read_mprofile_description): New
function.
* arm-tdep.h (arm_read_description)
(arm_read_mprofile_description): Add declaration.
* configure.tgt: Add new files.
Both targets were using a mixture of defines and hardcoded values.
Add a standard set in arch/arm.h and use throughout, ensuring that
none of the existing sizes change.
No functionality changes.
gdb/ChangeLog:
* aarch32-linux-nat.h (VFP_REGS_SIZE): Remove define.
* aarch64-linux-nat.c (fetch_fpregs_from_thread)
(store_fpregs_to_thread)
(aarch64_linux_nat_target::read_description): Use ARM_VFP3_REGS_SIZE.
* arch/arm.h (IWMMXT_VEC_REGISTER_SIZE, ARM_CORE_REGS_SIZE)
(ARM_FP_REGS_SIZE, ARM_VFP2_REGS_SIZE, ARM_VFP3_REGS_SIZE)
(IWMMXT_REGS_SIZE): Add define.
* arm-linux-nat.c (IWMMXT_REGS_SIZE): Remove define.
(fetch_vfp_regs, store_vfp_regs)
(arm_linux_nat_target::read_description): Use ARM_VFP3_REGS_SIZE.
* arm-tdep.c (arm_register_g_packet_guesses): Use new defines.
gdb/gdbserver/ChangeLog:
* linux-aarch32-low.c (arm_read_description, arm_regsets): Use new
defines.
* linux-arm-low.c (arm_read_description, arm_regsets): Likewise.
Add ARM_ to the front of INT_REGISTER_SIZE, FP_REGISTER_SIZE and
ARM_VFP_REGISTER_SIZE to make it obvious they are for the Arm target.
Move the defines to arch/arm.h
No functionality changes.
gdb/ChangeLog:
* arch/arm-get-next-pcs.c (thumb_get_next_pcs_raw): Use ARM_
defines.
* arch/arm-linux.c (arm_linux_sigreturn_next_pc_offset): Likewise.
* arch/arm.h (INT_REGISTER_SIZE) Rename from...
(ARM_INT_REGISTER_SIZE): ...to this.
(ARM_FP_REGISTER_SIZE) (ARM_VFP_REGISTER_SIZE): Add define.
* arm-linux-tdep.c (ARM_LINUX_JB_ELEMENT_SIZE)
(ARM_LINUX_SIZEOF_GREGSET, arm_linux_supply_gregset)
(arm_linux_collect_gregset, supply_nwfpe_register)
(collect_nwfpe_register, arm_linux_collect_nwfpe): Use ARM_
defines.
* arm-linux-tdep.h (ARM_LINUX_SIZEOF_NWFPE, NWFPE_FPSR_OFFSET)
(NWFPE_FPCR_OFFSET, NWFPE_TAGS_OFFSET): Likewise
* arm-nbsd-tdep.c (ARM_NBSD_JB_ELEMENT_SIZE): Likewise.
* arm-tdep.c (arm_push_dummy_call, arm_extract_return_value)
(arm_return_in_memory, arm_store_return_value)
(arm_get_longjmp_target, arm_register_g_packet_guesses)
(arm_record_ld_st_multiple): Likewise.
* arm-tdep.h (FP_REGISTER_SIZE, VFP_REGISTER_SIZE): Remove.
* arm-wince-tdep.c (ARM_WINCE_JB_ELEMENT_SIZE): Use ARM_ defines.
Add the pauth registers to the regset lists.
Add a new regset type OPTIONAL_REGS which allows for the regset read to fail.
Once the read fails, it will not be checked again. This allows targets with
optional features to keep a single static regset_info structure.
gdb/ChangeLog:
* arch/aarch64.h (AARCH64_PAUTH_REGS_SIZE): New define.
gdb/gdbserver/ChangeLog:
* linux-aarch64-low.c (aarch64_store_pauthregset): New function.
* linux-low.c (regsets_store_inferior_registers): Allow optional reads
to fail.
* linux-low.h (enum regset_type): Add OPTIONAL_REGS.
Initialise the pauth registers when creating a target description, and store
the regnum of the first pauth register.
Use ptrace to read the registers in the pauth feature.
Do not allow the registers to be written.
gdb/ChangeLog:
* aarch64-linux-nat.c (fetch_pauth_masks_from_thread): New
function.
(aarch64_linux_nat_target::fetch_registers): Read pauth registers.
* aarch64-tdep.c (aarch64_cannot_store_register): New function.
(aarch64_gdbarch_init): Add puth registers.
* aarch64-tdep.h (struct gdbarch_tdep): Add pauth features.
* arch/aarch64.h (AARCH64_PAUTH_DMASK_REGNUM): New define.
(AARCH64_PAUTH_CMASK_REGNUM): Likewise.
Pointer Authentication is a new feature in AArch64 v8.3-a. When enabled in
the compiler, function return addresses will be mangled by the kernel.
Add register description xml and wire up to aarch64_linux_read_description.
This description includes the two pauth user registers.
Nothing yet uses the feature - that is added in later patches.
gdb/ChangeLog:
* aarch64-linux-nat.c
(aarch64_linux_nat_target::read_description): Add pauth param.
* aarch64-linux-tdep.c
(aarch64_linux_core_read_description): Likewise.
* aarch64-tdep.c (struct target_desc): Add in pauth.
(aarch64_read_description): Add pauth param.
(aarch64_gdbarch_init): Likewise.
* aarch64-tdep.h (aarch64_read_description): Likewise.
* arch/aarch64.c (aarch64_create_target_description): Likewise.
* arch/aarch64.h (aarch64_create_target_description): Likewise.
* features/Makefile: Add new files.
* features/aarch64-pauth.c: New file.
* features/aarch64-pauth.xml: New file.
gdb/doc/ChangeLog:
* gdb.texinfo: Describe pauth feature.
gdb/gdbserver/ChangeLog:
* linux-aarch64-ipa.c (get_ipa_tdesc): Add pauth param.
(initialize_low_tracepoint): Likewise.
* linux-aarch64-low.c (aarch64_arch_setup): Likewise.
* linux-aarch64-tdesc-selftest.c (aarch64_tdesc_test): Likewise.
* linux-aarch64-tdesc.c (struct target_desc): Likewise.
(aarch64_linux_read_description): Likewise.
* linux-aarch64-tdesc.h (aarch64_linux_read_description): Likewise.
As on amd64, these registers hold the base address of the fs and gs
segments, respectively. For i386 these two registers are 32 bits.
gdb/ChangeLog:
* amd64-fbsd-nat.c (amd64_fbsd_nat_target::read_description):
Update calls to i386_target_description to add 'segments'
parameter.
* amd64-tdep.c (amd64_init_abi): Set tdep->fsbase_regnum. Don't
add segment base registers.
* arch/i386.c (i386_create_target_description): Add 'segments'
parameter to enable segment base registers.
* arch/i386.h (i386_create_target_description): Likewise.
* features/i386/32bit-segments.xml: New file.
* features/i386/32bit-segments.c: Generate.
* i386-fbsd-nat.c (i386_fbsd_nat_target::read_description): Update
call to i386_target_description to add 'segments' parameter.
* i386-fbsd-tdep.c (i386fbsd_core_read_description): Likewise.
* i386-go32-tdep.c (i386_go32_init_abi): Likewise.
* i386-linux-tdep.c (i386_linux_read_description): Likewise.
* i386-tdep.c (i386_validate_tdesc_p): Add segment base registers
if feature is present.
(i386_gdbarch_init): Pass I386_NUM_REGS to set_gdbarch_num_regs.
Add 'segments' parameter to call to i386_target_description.
(i386_target_description): Add 'segments' parameter to enable
segment base registers.
(_initialize_i386_tdep) [GDB_SELF_TEST]: Add 'segments' parameter
to call to i386_target_description.
* i386-tdep.h (struct gdbarch_tdep): Add 'fsbase_regnum'.
(enum i386_regnum): Add I386_FSBASE_REGNUM and I386_GSBASE_REGNUM.
Define I386_NUM_REGS.
(i386_target_description): Add 'segments' parameter to enable
segment base registers.
gdb/gdbserver/ChangeLog:
* linux-x86-tdesc.c (i386_linux_read_description): Update call to
i386_create_target_description for 'segments' parameter.
* lynx-i386-low.c (lynx_i386_arch_setup): Likewise.
* nto-x86-low.c (nto_x86_arch_setup): Likewise.
* win32-i386-low.c (i386_arch_setup): Likewise.
While working on my other scripts to deal with gdb headers, I noticed
that some files were missing include guards. I wrote a script to add
the missing ones, but found that using the obvious names for the
guards ran into clashes -- for example, gdb/nat/linux-nat.h used
"LINUX_NAT_H", but this was also the script's choice for
gdb/linux-nat.h.
So, I changed the script to normalize all include guards in gdb. This
patch is the result.
As usual the script is available here:
https://github.com/tromey/gdb-refactoring-scripts
Tested by rebuilding; I also ran it through "Fedora-x86_64-m64" on the
buildbot.
gdb/ChangeLog
2019-02-07 Tom Tromey <tom@tromey.com>
* yy-remap.h: Add include guard.
* xtensa-tdep.h: Add include guard.
* xcoffread.h: Rename include guard.
* varobj-iter.h: Add include guard.
* tui/tui.h: Rename include guard.
* tui/tui-winsource.h: Rename include guard.
* tui/tui-wingeneral.h: Rename include guard.
* tui/tui-windata.h: Rename include guard.
* tui/tui-win.h: Rename include guard.
* tui/tui-stack.h: Rename include guard.
* tui/tui-source.h: Rename include guard.
* tui/tui-regs.h: Rename include guard.
* tui/tui-out.h: Rename include guard.
* tui/tui-layout.h: Rename include guard.
* tui/tui-io.h: Rename include guard.
* tui/tui-hooks.h: Rename include guard.
* tui/tui-file.h: Rename include guard.
* tui/tui-disasm.h: Rename include guard.
* tui/tui-data.h: Rename include guard.
* tui/tui-command.h: Rename include guard.
* tic6x-tdep.h: Add include guard.
* target/waitstatus.h: Rename include guard.
* target/wait.h: Rename include guard.
* target/target.h: Rename include guard.
* target/resume.h: Rename include guard.
* target-float.h: Rename include guard.
* stabsread.h: Add include guard.
* rs6000-tdep.h: Add include guard.
* riscv-fbsd-tdep.h: Add include guard.
* regformats/regdef.h: Rename include guard.
* record.h: Rename include guard.
* python/python.h: Rename include guard.
* python/python-internal.h: Rename include guard.
* python/py-stopevent.h: Rename include guard.
* python/py-ref.h: Rename include guard.
* python/py-record.h: Rename include guard.
* python/py-record-full.h: Rename include guard.
* python/py-record-btrace.h: Rename include guard.
* python/py-instruction.h: Rename include guard.
* python/py-events.h: Rename include guard.
* python/py-event.h: Rename include guard.
* procfs.h: Add include guard.
* proc-utils.h: Add include guard.
* p-lang.h: Add include guard.
* or1k-tdep.h: Rename include guard.
* observable.h: Rename include guard.
* nto-tdep.h: Rename include guard.
* nat/x86-linux.h: Rename include guard.
* nat/x86-linux-dregs.h: Rename include guard.
* nat/x86-gcc-cpuid.h: Add include guard.
* nat/x86-dregs.h: Rename include guard.
* nat/x86-cpuid.h: Rename include guard.
* nat/ppc-linux.h: Rename include guard.
* nat/mips-linux-watch.h: Rename include guard.
* nat/linux-waitpid.h: Rename include guard.
* nat/linux-ptrace.h: Rename include guard.
* nat/linux-procfs.h: Rename include guard.
* nat/linux-osdata.h: Rename include guard.
* nat/linux-nat.h: Rename include guard.
* nat/linux-namespaces.h: Rename include guard.
* nat/linux-btrace.h: Rename include guard.
* nat/glibc_thread_db.h: Rename include guard.
* nat/gdb_thread_db.h: Rename include guard.
* nat/gdb_ptrace.h: Rename include guard.
* nat/fork-inferior.h: Rename include guard.
* nat/amd64-linux-siginfo.h: Rename include guard.
* nat/aarch64-sve-linux-sigcontext.h: Rename include guard.
* nat/aarch64-sve-linux-ptrace.h: Rename include guard.
* nat/aarch64-linux.h: Rename include guard.
* nat/aarch64-linux-hw-point.h: Rename include guard.
* mn10300-tdep.h: Add include guard.
* mips-linux-tdep.h: Add include guard.
* mi/mi-parse.h: Rename include guard.
* mi/mi-out.h: Rename include guard.
* mi/mi-main.h: Rename include guard.
* mi/mi-interp.h: Rename include guard.
* mi/mi-getopt.h: Rename include guard.
* mi/mi-console.h: Rename include guard.
* mi/mi-common.h: Rename include guard.
* mi/mi-cmds.h: Rename include guard.
* mi/mi-cmd-break.h: Rename include guard.
* m2-lang.h: Add include guard.
* location.h: Rename include guard.
* linux-record.h: Rename include guard.
* linux-nat.h: Add include guard.
* linux-fork.h: Add include guard.
* i386-darwin-tdep.h: Rename include guard.
* hppa-linux-offsets.h: Add include guard.
* guile/guile.h: Rename include guard.
* guile/guile-internal.h: Rename include guard.
* gnu-nat.h: Rename include guard.
* gdb-stabs.h: Rename include guard.
* frv-tdep.h: Add include guard.
* f-lang.h: Add include guard.
* event-loop.h: Add include guard.
* darwin-nat.h: Rename include guard.
* cp-abi.h: Rename include guard.
* config/sparc/nm-sol2.h: Rename include guard.
* config/nm-nto.h: Rename include guard.
* config/nm-linux.h: Add include guard.
* config/i386/nm-i386gnu.h: Rename include guard.
* config/djgpp/nl_types.h: Rename include guard.
* config/djgpp/langinfo.h: Rename include guard.
* compile/gcc-cp-plugin.h: Add include guard.
* compile/gcc-c-plugin.h: Add include guard.
* compile/compile.h: Rename include guard.
* compile/compile-object-run.h: Rename include guard.
* compile/compile-object-load.h: Rename include guard.
* compile/compile-internal.h: Rename include guard.
* compile/compile-cplus.h: Rename include guard.
* compile/compile-c.h: Rename include guard.
* common/xml-utils.h: Rename include guard.
* common/x86-xstate.h: Rename include guard.
* common/version.h: Rename include guard.
* common/vec.h: Rename include guard.
* common/tdesc.h: Rename include guard.
* common/selftest.h: Rename include guard.
* common/scoped_restore.h: Rename include guard.
* common/scoped_mmap.h: Rename include guard.
* common/scoped_fd.h: Rename include guard.
* common/safe-iterator.h: Rename include guard.
* common/run-time-clock.h: Rename include guard.
* common/refcounted-object.h: Rename include guard.
* common/queue.h: Rename include guard.
* common/ptid.h: Rename include guard.
* common/print-utils.h: Rename include guard.
* common/preprocessor.h: Rename include guard.
* common/pathstuff.h: Rename include guard.
* common/observable.h: Rename include guard.
* common/netstuff.h: Rename include guard.
* common/job-control.h: Rename include guard.
* common/host-defs.h: Rename include guard.
* common/gdb_wait.h: Rename include guard.
* common/gdb_vecs.h: Rename include guard.
* common/gdb_unlinker.h: Rename include guard.
* common/gdb_unique_ptr.h: Rename include guard.
* common/gdb_tilde_expand.h: Rename include guard.
* common/gdb_sys_time.h: Rename include guard.
* common/gdb_string_view.h: Rename include guard.
* common/gdb_splay_tree.h: Rename include guard.
* common/gdb_setjmp.h: Rename include guard.
* common/gdb_ref_ptr.h: Rename include guard.
* common/gdb_optional.h: Rename include guard.
* common/gdb_locale.h: Rename include guard.
* common/gdb_assert.h: Rename include guard.
* common/filtered-iterator.h: Rename include guard.
* common/filestuff.h: Rename include guard.
* common/fileio.h: Rename include guard.
* common/environ.h: Rename include guard.
* common/common-utils.h: Rename include guard.
* common/common-types.h: Rename include guard.
* common/common-regcache.h: Rename include guard.
* common/common-inferior.h: Rename include guard.
* common/common-gdbthread.h: Rename include guard.
* common/common-exceptions.h: Rename include guard.
* common/common-defs.h: Rename include guard.
* common/common-debug.h: Rename include guard.
* common/cleanups.h: Rename include guard.
* common/buffer.h: Rename include guard.
* common/btrace-common.h: Rename include guard.
* common/break-common.h: Rename include guard.
* cli/cli-utils.h: Rename include guard.
* cli/cli-style.h: Rename include guard.
* cli/cli-setshow.h: Rename include guard.
* cli/cli-script.h: Rename include guard.
* cli/cli-interp.h: Rename include guard.
* cli/cli-decode.h: Rename include guard.
* cli/cli-cmds.h: Rename include guard.
* charset-list.h: Add include guard.
* buildsym-legacy.h: Rename include guard.
* bfin-tdep.h: Add include guard.
* ax.h: Rename include guard.
* arm-linux-tdep.h: Add include guard.
* arm-fbsd-tdep.h: Add include guard.
* arch/xtensa.h: Rename include guard.
* arch/tic6x.h: Add include guard.
* arch/i386.h: Add include guard.
* arch/arm.h: Rename include guard.
* arch/arm-linux.h: Rename include guard.
* arch/arm-get-next-pcs.h: Rename include guard.
* arch/amd64.h: Add include guard.
* arch/aarch64-insn.h: Rename include guard.
* arch-utils.h: Rename include guard.
* annotate.h: Add include guard.
* amd64-darwin-tdep.h: Rename include guard.
* aarch64-linux-tdep.h: Add include guard.
* aarch64-fbsd-tdep.h: Add include guard.
* aarch32-linux-nat.h: Add include guard.
gdb/gdbserver/ChangeLog
2019-02-07 Tom Tromey <tom@tromey.com>
* x86-tdesc.h: Rename include guard.
* x86-low.h: Add include guard.
* wincecompat.h: Rename include guard.
* win32-low.h: Add include guard.
* utils.h: Rename include guard.
* tracepoint.h: Rename include guard.
* tdesc.h: Rename include guard.
* target.h: Rename include guard.
* server.h: Rename include guard.
* remote-utils.h: Rename include guard.
* regcache.h: Rename include guard.
* nto-low.h: Rename include guard.
* notif.h: Add include guard.
* mem-break.h: Rename include guard.
* lynx-low.h: Add include guard.
* linux-x86-tdesc.h: Add include guard.
* linux-s390-tdesc.h: Add include guard.
* linux-ppc-tdesc-init.h: Add include guard.
* linux-low.h: Add include guard.
* linux-aarch64-tdesc.h: Add include guard.
* linux-aarch32-low.h: Add include guard.
* inferiors.h: Rename include guard.
* i387-fp.h: Rename include guard.
* hostio.h: Rename include guard.
* gdbthread.h: Rename include guard.
* gdb_proc_service.h: Rename include guard.
* event-loop.h: Rename include guard.
* dll.h: Rename include guard.
* debug.h: Rename include guard.
* ax.h: Rename include guard.
The goal of this commit is to allow RV64 binaries compiled for the 'F'
extension to run on a target that supports both the 'F' and 'D'
extensions.
The 'D' extension depends on the 'F' extension and chapter 9 of the
RISC-V ISA manual implies that running a program compiled for 'F' on
a 'D' target should be fine.
To support this the gdbarch now holds two feature sets, one represents
the features that are present on the target, and one represents the
features requested in the ELF flags.
The existing error checks are relaxed slightly to allow binaries
compiled for 32-bit 'F' extension to run on targets with the 64-bit
'D' extension.
A new set of functions called riscv_abi_{xlen,flen} are added to
compliment the existing riscv_isa_{xlen,flen}, and some callers to the
isa functions now call the abi functions when that is appropriate.
In riscv_call_arg_struct two asserts are removed, these asserts no
longer make sense. The asserts were both like this:
gdb_assert (TYPE_LENGTH (ainfo->type)
<= (cinfo->flen + cinfo->xlen));
And were made in two cases, when passing structures like these:
struct {
integer field1;
float field2;
};
or,
struct {
float field1;
integer field2;
};
When running on an RV64 target which only has 32-bit float then the
integer field could be 64-bits, while if the float field is 32-bits
the overall size of the structure can be 128-bits (with 32-bits of
padding). In this case the assertion would fail, however, the code
isn't incorrect, so its safe to just remove the assertion.
This was tested by running on an RV64IMFDC target using a compiler
configured for RV64IMFC, and comparing the results with those obtained
when using a compiler configured for RV64IMFDC. The only regressions
I see (now) are in gdb.base/store.exp and are related too different
code generation choices GCC makes between the two targets.
Finally, this commit does not make any attempt to support running
binaries compiled for RV32 on an RV64 target, though nothing in here
should prevent that being supported in the future.
gdb/ChangeLog:
* arch/riscv.h (struct riscv_gdbarch_features) <hw_float_abi>:
Delete.
<operator==>: Update with for removed field.
<hash>: Likewise.
* riscv-tdep.h (struct gdbarch_tdep) <features>: Renamed to...
<isa_features>: ...this.
<abi_features>: New field.
(riscv_isa_flen): Update comment.
(riscv_abi_xlen): New declaration.
(riscv_abi_flen): New declaration.
* riscv-tdep.c (riscv_isa_xlen): Update to get answer from
isa_features.
(riscv_abi_xlen): New function.
(riscv_isa_flen): Update to get answer from isa_features.
(riscv_abi_flen): New function.
(riscv_has_fp_abi): Update to get answer from abi_features.
(riscv_call_info::riscv_call_info): Use abi xlen and flen, not isa
xlen and flen.
(riscv_call_info) <xlen, flen>: Update comment.
(riscv_call_arg_struct): Remove invalid assertions
(riscv_features_from_gdbarch_info): Update now hw_float_abi field
is removed.
(riscv_gdbarch_init): Gather isa features and abi features
separately, ensure both match on the gdbarch when reusing an old
gdbarch. Relax an error check to allow 32-bit abi float to run on
a target with 64-bit float hardware.
This commit applies all changes made after running the gdb/copyright.py
script.
Note that one file was flagged by the script, due to an invalid
copyright header
(gdb/unittests/basic_string_view/element_access/char/empty.cc).
As the file was copied from GCC's libstdc++-v3 testsuite, this commit
leaves this file untouched for the time being; a patch to fix the header
was sent to gcc-patches first.
gdb/ChangeLog:
Update copyright year range in all GDB files.
GDB relies on the fact that if two target descriptions have the same
contents, then they will be the same object instance (having the same
address). One place where this is a requirement is in
GDBARCH_LIST_LOOKUP_BY_INFO which is used to find previously created
gdbarch objects.
In GDBARCH_LIST_LOOKUP_BY_INFO a pointer comparison is made on the
gdbarch's target description, if the pointers are different then it is
assumed the gdbarches have different, non-compatible target
descriptions.
Previously we would create duplicate target descriptions in the belief
that RISCV_GDBARCH_INIT would spot this duplication and discard the
second instance. However, this was incorrect, and instead we ended up
creating duplicate gdbarch objects.
With this commit every unique feature set will create one and only one
target description, the feature set and resulting target description
is then cached so that the same target description object can be
returned later.
Many other target avoid this problem by creating a small number of
named target descriptions, and returning one of these. However, we
currently have 8 possible target descriptions (32 vs 64 bit for x-reg
and f-reg, and h/w or s/w float abi) and creating each of these just
to avoid a dynamic cache seems pointless.
gdb/ChangeLog:
* arch/riscv.h (riscv_gdbarch_features::hash): New method.
* arch/riscv.c (struct riscv_gdbarch_features_hasher): New.
(riscv_tdesc_cache): New global.
(riscv_create_target_description): Look in the cache before
creating a new target description.
Add '==' and '!=' operators for the struct riscv_gdb_features,
allowing a small simplification.
gdb/ChangeLog:
* arch/riscv.h (riscv_gdb_features::operator==): New.
(riscv_gdb_features::operator!=): New.
* riscv-tdep.c (riscv_gdbarch_init): Make use of the inequality
operator.
Makes more of the interface related to fetching target descriptions
constant.
gdb/ChangeLog:
* arch/riscv.h (riscv_create_target_description): Make return type
const.
* arch/riscv.c (riscv_create_target_description): Likewise.
* riscv-tdep.c (riscv_find_default_target_description): Likewise.
Simon Marchi
Luis Machado
Srinath Parvathaneni
Andrew Burgess
Matthew Malcomson
Joel Brobecker
Simon Marchi
Shahab Vahedi
Tom de Vries
Anton Kolesov
Christian Biesinger
Ulrich Weigand
Alan Hayward
Tom Tromey
John Baldwin